A Gaussian Mixture Model Clustering Ensemble Regressor for Semiconductor Manufacturing Final Test Yield Prediction

Abstract

In the semiconductor industry, many studies have been carried out for front-end related process improvement and yield prediction using machine learning techniques. However, very few research investigations have dealt with the backend Final Test (FT) yield prediction using the front-end wafer acceptance test (WAT) parameters. The manufacturing cycle time between wafer fabrication (WF) and FT can range anywhere between a few weeks to several months. It is therefore important for semiconductor manufacturers to detect wafer material related low yield problems at an earlier stage for effective cost and quality control. This is a challenging goal as the input data used for prediction is at a very early manufacturing stage and the output FT yield for packaged chips is the last stage of the fabrication chain. There are many unknown production variations caused by different manufacturing processes, equipment configurations and human interferences in this multi-stage sequential fabrication chain. In this paper, we proposed a novel procedure to predict the backend FT yield at the WF stage itself using a Gaussian Mixture Models (GMM) clustering approach that is applied to build a weighted ensemble regressor. Real production data for new chip product lines are verified with this method and show significant improvement in the prediction performance.

Semiconductor Manufacturing Final Test Yield Optimization and Wafer Acceptance Test Parameter Inverse Design Using Multi-Objective Optimization Algorithms

“…In our previous work [1], [22], FT yield prediction framework using WAT parameters was introduced and feature importance analysis was applied to identify the root cause (WAT parameter) for low yield samples (sub-population). In this work, we will continue the work in [1], [22] to provide actionable solutions for FT yield improvements through WAT parameter inverse design.…”

“…In our previous work [1], [22], FT yield prediction framework using WAT parameters was introduced and feature importance analysis was applied to identify the root cause (WAT parameter) for low yield samples (sub-population). In this work, we will continue the work in [1], [22] to provide actionable solutions for FT yield improvements through WAT parameter inverse design. To the best of our knowledge, this is the first study aimed at improving semiconductor manufacturing FT yield through WAT parameter inverse design by means of using multi-objective optimization algorithms.…”

“…1. The details of the central portion in the flow chart, referred to as "machine learning yield prediction model", is presented in sufficient detail in our previous work, [22]. In this study, we focus on the right portion -yield optimization and WAT parameter inverse design.…”

“…The time duration between WF and FT can take up to several months. Therefore, it is important to detect FT low yield problem at the WF stage itself for economic reasons and also to ensure robust quality control as mentioned in [1], [22]. At the WF stage, using the production FT yield and WAT data, a machine learning FT yield prediction model is generated and five key WAT parameters are identified based on feature importance analysis.…”

“…In the generated FT yield prediction model, the WAT parameters are normalized using population mean and standard deviation as mentioned in [22]. Therefore, x stands for the important WAT parameters' sigma shift value.…”