A general co-design approach to multi-level package modeling based on individual single-level package full-wave S-parameter modeling including signal and power/ground ports

Chen, Zhaoqing

doi:10.1109/ectc.2012.6249066

Cited by 11 publications

(6 citation statements)

References 9 publications

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“…In Figs. 16-19, the outer ports are not de-embedded so that the Sparameter curves have some basic difference from the ones in [7] with all ports, including the inner ports and outer ports, are de-embedded by the negative capacitance method [8].…”

Section: Verification and Applicationmentioning

confidence: 99%

“…The figures also show that the curves without lumped/discrete port de-embedding have too large error. The second test case is a module-board-module structure (Fig.14) as used in [7]. For simplicity, a smaller printed circuit board is used to replace each module.…”

Section: Verification and Applicationmentioning

confidence: 99%

“…Some special lumped port with realistic, not artificial, parasitic parameters like the circular lumped port is suitable only in some particular cases such as the port defined at via clearance hole location, for example. In this paper, the gap lumped/discrete port (Fig.2) as defined at the natural boundaries of different chip/package components in [7] is used for good port connectivity since not only the port signal node pair (e.g. Node Pairs S AB1 -S BA1 , S AB2 -S BA2 , and S AB3 -S BA3 in Fig.2) but also the port reference node pair (e.g.…”

Section: Introductionmentioning

confidence: 99%

“…The ports defined in the model can be either signal ports only or general ports including all signal and power/ground ports [7]. The port definitions should be the consistent on the two ports of a connected port pair so that not only the signal nodes but also the reference notes (local ground) of the two ports are connected electrically.…”

Section: Introductionmentioning

confidence: 99%

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A lumped/discrete port de-embedding method by port connection error-cancelling network in full-wave electromagnetic modeling of 3D integration and packaging with vertical interconnects

Chen

2013

2013 IEEE 63rd Electronic Components and Technology Conference

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In t his pap er, a lu mped/d iscret e po rt de-embedd ing method by port connection error-cancelling network is proposed for full-wave modeling interconnect and packaging co mpo ne nt s w it h bu mp/p in arra y int er fac es in 3D int egrat io n as well as conventional packaging systems. This method is based on the S-parameter matrix operation. Three calibration structures are simulated for extraction of the error-cancelling network. This error-cancelling network is inserted into the physical port connection interface in system SI simulation to cancel the port connection error caused by the port parasitic parameters and the uncertainty in port voltage and current definitions. Theoretically this method is a wide-band approach valid on every frequency point included in the S-parameter model. This approach is verified by two application examples with signal, power, and ground ports for power-aware SI applications including a 20-port 9-chip stack connected by TSV's, a 20-port module-board-module structure, and the third example of a 36-signal-port printed circuit board via array for conventional SI applications. The connection error of cascaded physical networks after de-embedding by inserting the proposed error-cancelling network at the physical connection location is much smaller than the one without de-embedding.

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Section: Verification and Applicationmentioning

confidence: 99%

Section: Verification and Applicationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A lumped/discrete port de-embedding method by port connection error-cancelling network in full-wave electromagnetic modeling of 3D integration and packaging with vertical interconnects

Chen

2013

2013 IEEE 63rd Electronic Components and Technology Conference

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“…The next approach is based on the methodology presented in [9]. The reader is encouraged to review the cited reference for more in-depth information on the methodology.…”

Section: Chip-interposer Co-analysis: 25d Link Examplementioning

confidence: 99%

3D IC-package-board co-analysis using 3D EM simulation for mobile applications

Kostka

Song

Lim

2013

2013 IEEE 63rd Electronic Components and Technology Conference

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3D IC based systems necessitate a chip-package co-design approach since the TSV response in the chip stack can propagate into the package. In this work, we demonstrate a chip-interposer co-analysis methodology that includes the 3D CAD model of the 3D IC and compare this to the conventional analysis techniques. Our findings demonstrate that the coupling between signal TSV's in the chip stack has a significant impact on the overall channel response and needs to be carefully modeled in order to obtain accurate results. BackgroundOver the past decade, the trend in the consumer electronics industry has been to develop high performance multifunctional products with a compact size and reduced cost. Modern systems demand new technologies that can integrate RF, analog, digital and sensor functionalities while maintaining minimal interference among different systems. Multi-functional integration can be achieved by stacking multiple chips vertically (3D IC). 3D ICs promise more than Moore integration by packing many functions into a small form factor. To implement 3D IC technology, requires chip to chip interposers as well as through silicon vias (TSVs) [1]- [6].For 3D IC technology, a chip-package co-design approach is necessary since the TSV response in the chip stack can propagate into the package. With respect to 3D ICs which are stacked using TSVs, crosstalk is a major concern especially in the case of dense TSV arrays, not only in signal nets, but also in the power delivery network (PDN) as well. It has been demonstrated that the crosstalk waveform exhibits a distinct RC behavior leading to a slow decay of the coupled waveform, which is unique to TSVs [1]- [2]. This RC effect can be quite detrimental since it can create inter symbol interference (ISI). Memory interfaces also require a co-design approach. These interfaces are currently designed to support single-ended data rates in the 1GHz-plus range, and serial links are running upwards of 10 Gb/s. This necessitates a precise design analysis and rules-based control of each of these signals at the die, package and PCB levels. However when chip, package and board power delivery components are designed separately, there is no opportunity to optimize the global PDN and once these are connected together, this could produce unexpected results.In this work, we demonstrate a chip-package co-analysis methodology that includes the 3D CAD model of the 3D IC and compare this to the conventional analysis approach which is to represent the IC using either IBIS or SPICE equivalent models. To demonstrate the co-design methodology, we consider two realistic test cases for mobile applications in this work. The first is composed of a 2.5D silicon interposer

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High-Speed Circuit Power Integrity Design Based on Impedance Characteristic Analysis

Zhang

2019

Communications in Computer and Information Science

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A general co-design approach to multi-level package modeling based on individual single-level package full-wave S-parameter modeling including signal and power/ground ports

Cited by 11 publications

References 9 publications

A lumped/discrete port de-embedding method by port connection error-cancelling network in full-wave electromagnetic modeling of 3D integration and packaging with vertical interconnects

A lumped/discrete port de-embedding method by port connection error-cancelling network in full-wave electromagnetic modeling of 3D integration and packaging with vertical interconnects

3D IC-package-board co-analysis using 3D EM simulation for mobile applications

High-Speed Circuit Power Integrity Design Based on Impedance Characteristic Analysis

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