A General gm/Id Temperature-Aware Design Methodology Using 180 nm CMOS up to 250 °C

Abstract

The advent of the Internet-of-Things brings new challenges in circuit design. The presence of circuits and sensors in harsh environments brought the need for methodologies that account for them. Since the beginning of the transistors, the temperature is known for having a significant impact on performance, and even though very low temperature sensitivity circuits have been proposed, no general methodology for designing them exists. This paper proposes a general gm over Id technique for designing temperature-aware circuits that can be used either on measurement data, analytically, or based on simulation models. This model is validated using measurements up to 250°C of X-FAB XT018 transistors and later with a circuit design example.

A 5-DC-parameter MOSFET model for circuit simulation in QucsStudio and SPECTRE

“…To incorporate the temperature variation in the simulation model, fitting curves were found for each parameter. The threshold voltage dependence on the temperature, which is linear as expected from its physical definition [13] - [14], is given by (9).…”

Design Criteria of High-Temperature Integrated Circuits Using Standard SOI CMOS Process up to 300°C

“…The work in [20] instead is more oriented to the design techniques for high temperature circuits, based on 𝑔 𝑚 /𝐼 𝑑 methodology for Zero Temperature Coefficient (ZTC) biasing. The following work [21] by the same group extends the proposed design methodology up to an operation temperature of 250°C, assessing the functionality with chip measurements on a Voltage Controlled Oscillator. A temperaturedependent SOI MOSFET compact model has been developed in [22], considering the existing temperature dependence of device parameters, but only for long-channel MOSFETs based on old technology processes.…”