A General Hardware/Software Co-design Methodology for Embedded Signal Processing and Multimedia Workloads

Brogioli, Michael C.; Radosavljevic, Predrag; Cavallaro, Joseph R.

doi:10.1109/acssc.2006.355005

Cited by 10 publications

(6 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As an example, using the workload partition criteria for partitioning functionality between a programmable DSP core and system containing multiple hardware for a 3.5G HSDPA system, it has been shown that impressive performance results can be obtained. In studying the bottlenecks of such systems when implemented on a programmable DSP core in software, it has been found the key bottlenecks in the system to be the channel estimation, fast fourier transform (FFT), inverse fast fourier transform (IFFT), FIR filter, and to a lesser extent despreading and descrambling as illustrated in Figure 4 [9]. By migrating the 3.5G implementation from a solely software based implementation executing on a TMS320C64x based programmable DSP core to a heterogeneous system containing not only programmable DSP cores but also distinct hardware acceleration for the various bottlenecks, the authors achieve almost an 11.2x speedup in the system [9].…”

Section: Mimo Channel Equalization Acceleratormentioning

confidence: 99%

Application-Specific Accelerators for Communications

Tarver

Sun

Amiri

et al. 2018

Handbook of Signal Processing Systems

Self Cite

View full text Add to dashboard Cite

For computation-intensive digital signal processing algorithms, complexity is exceeding the processing capabilities of general-purpose digital signal processors (DSPs). In some of these applications, DSP hardware accelerators have been widely used to off-load a variety of algorithms from the main DSP host, including FFT, FIR/IIR filters, multiple-input multiple-output (MIMO) detectors, and error correction codes (Viterbi, Turbo, LDPC) decoders. Given power and cost considerations, simply implementing these computationally complex parallel algorithms with high-speed general-purpose DSP processor is not very efficient. However, not all DSP algorithms are appropriate for off-loading to a hardware accelerator. First, these algorithms should have data-parallel computations and repeated operations that are amenable to hardware implementation. Second, these algorithms should have a deterministic dataflow graph that maps to parallel datapaths. The accelerators that we consider are mostly coarse grain to better deal with streaming data transfer for achieving both high performance and low power. In this chapter, we focus on some of the basic and advanced digital signal processing algorithms for communications and cover major examples of DSP accelerators for communications.

show abstract

Section: Mimo Channel Equalization Acceleratormentioning

confidence: 99%

Application-Specific Accelerators for Communications

Tarver

Sun

Amiri

et al. 2018

Handbook of Signal Processing Systems

Self Cite

View full text Add to dashboard Cite

show abstract

“…Several studies have addressed the task portioning of signal processing functions for wireless receivers [20,21]. However, these studies focus on projecting a single communication mode into the heterogeneous processing architecture.…”

Section: Software Defined Radio Architecturementioning

confidence: 99%

Adaptability and Configurability in Cognitive Radio Design on Small Form Factor Software Radio Platform

Tachwali

Basma

Refai

2010

Wireless Pers Commun

View full text Add to dashboard Cite

The recent advances in cognitive radio technology based on software defined radio platforms have extended the capabilities of wireless communication systems. The unique ability of cognitive radios to alter their communication protocols to meet changing system demands make them great candidates for wireless applications that are difficult to implement using conventional wireless terminals. Small form factor platforms make cognitive radio portable and easy to deploy. This paper discusses the design and implementation methodology to build a cognitive radio on small form factor platform with heterogeneous processing architecture. The result of this discussion is a configurable wireless transceiver that features two important concepts of cognitive radio, namely configurability and adaptability.

show abstract

“…The task of system-level design is to trade-off an inexpensive and flexible software solution versus a high-speed hardware implementation. There are three main system level design approaches: hardware/ software co-design [9], platform-based design [10] and Model-driven Design [11]. Here the hardware refers to dedicated hardware component (ASIC) and Software refers to software executing on processor or ASIP.…”

Section: Introductionmentioning

confidence: 99%