A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits

Oughali, Feras Chikh

doi:10.1016/j.microrel.2013.09.002

Cited by 28 publications

(11 citation statements)

References 31 publications

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“…This result is due to the triplication of each module in the circuit. In comparison with the generalized modular redundancy scheme in [9], see that this technique has also a much larger area overhead (150%) compared to the area overhead of our proposed technique.…”

Section: E Comparison With Other Techniquesmentioning

confidence: 86%

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Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits

El-Maleh

Daud

2015

IEEE Trans. Rel.

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Due to current technology scaling trends, digital designs are becoming more sensitive to radiation-induced particle hits resulting from radioactivity decay and cosmic rays. A low-energy particle can flip the output of a gate, resulting in a soft error if it propagates to a circuit output. Thus, soft error tolerance has become an important criterion in digital system design. In this work, we propose a simulation-based approach to reduce the soft error probability of circuit failure in combinational logic circuits. The proposed method is based on maximizing the probability of logical masking when a soft error occurs. This maximization is done by extracting sub-circuits from an original multi-level circuit, and then re-synthesizing each extracted sub-circuit to increase fault masking against a single fault. We present a two-level synthesis scheme to maximize soft error masking on each extracted sub-circuit. This scheme provides a heuristic that finds the best set of cubes to cover the input patterns of an extracted sub-circuit. A Fast Extraction (FX) algorithm is used to enhance the area overhead of synthesized two-level sub-circuits. Experimental results on some MCNC combinational benchmarks show that, on average, a probability of circuit failure reduction of 32% is achieved compared to the original circuit. The average area overhead is 40% of the original circuit. Index Terms-Combinationalcircuit reliability, fault tolerance, single event transient, single event upset, soft errors. ACRONYMS AND ABBREVIATIONS SET single-event transient SEU single-event upset FX fast extraction CMOS complementary metal oxide semiconductor SER soft error rate TMR triple modular redundancy HICC history index of correct computation CDC controllability don't-care condition Vdd voltage drain-to-drain GND ground Manuscript

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Section: E Comparison With Other Techniquesmentioning

confidence: 86%

“…The most reliable unit is the unit with the highest history index. In [9], a generalized modular redundancy scheme is proposed for enhancing the fault tolerance of combinational circuits. In this technique, only the output combinations of the circuit with a high probability of occurrence are protected.…”

Section: A Hardware Redundancy-based Methodsmentioning

confidence: 99%

Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits

El-Maleh

Daud

2015

IEEE Trans. Rel.

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“…A generalized modular redundancy scheme has been presented in [17] to consider the probability of occurrence of each combination at the output of a circuit. The redundancy has been then added to only protect those combinations that have high probability of occurrence while the remaining combinations left unprotected to save area.…”

Section: Literature Reviewmentioning

confidence: 99%

Black box model-based self healing solution for stuck-at-faults in combinational circuits

Meyyappan

Alamelumangai

2017

IRASE

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The paper unveils a black box model-based self healing strategy to suppress the ill effects of stuck-at-faults occurring in combinational circuits. The primary theory endeavours to attach a sense of reliability in the performance of digital systems and makes them insensitive to the negative impact of faults present in the system. The proposed methodology employs a dynamic fault tolerant approach to protect digital systems from the incursion of stuck-at-faults and enables the system to come up with fault free outputs. The simulation results affi rm the authenticity of the proposed strategy to cancel out the infl uence of faults and facilitate the system to heal itself. The work utilizes the attributes of an FPGA to demonstrate the practical viability of the proposed approach. The performance analysis endorses the defi nite dominance of the proposed healing scheme over the traditional Triple Modular Redundancy [TMR] in terms of fault coverage and area overhead.

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“…Subsequent approaches attempt to insert redundancies that protect against the most common errors or to resynthesize the circuit to improve reliability. In [9], an approach is proposed to provide protection for the most common output combinations. In [10], the authors propose the use of implications to build redundant logic that checks for violation of behavioural constraints.…”

Section: Previous Workmentioning

confidence: 99%

Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches

et al. 2016

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Abstract-Technology scaling poses an increasing challenge to the reliability of digital circuits. Hardware redundancy solutions, such as Triple Modular Redundancy, produce very high area overhead, so partial redundancy is often used to reduce the overheads. Approximate logic circuits provide a general framework for optimized mitigation of errors arising from a broad class of failure mechanisms, including transient, intermittent and permanent failures. However, generating an optimal redundant logic circuit that is able to mask the faults with the highest probability while minimizing the area overheads is a challenging problem. In this work we propose and compare two new approaches to generate approximate logic circuits to be used in a TMR schema. The probabilistic approach approximates a circuit in a greedy manner based on a probabilistic estimation of the error. The evolutionary approach can provide radically different solutions that are hard to reach by other methods. By combining these two approaches, the solution space can be explored in depth. Experimental results demonstrate that the evolutionary approach can produce better solutions, but the probabilistic approach is close. On the other hand, these approaches provide much better scalability than other existing partial redundancy techniques.

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A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits

Cited by 28 publications

References 31 publications

Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits

Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits

Black box model-based self healing solution for stuck-at-faults in combinational circuits

Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches

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