A Graph‐Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions

Zaourar, Lilia; Kieffer, Yann; Aktouf, Chouki

doi:10.1155/2012/312808

Cited by 4 publications

(2 citation statements)

References 16 publications

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“…Future work should include liveness flags for addressable variables in order to reduce the memory-related context size. Another option could be to improve PSC construction by including scan-chain reordering [Zaourar et al 2012] and/or cost-free scans [Lin et al 1995]. Eventually, further research on how to limit the number of PSCs (to limit hardware overhead from multiplexors and dummy registers) while keeping a fast context extraction could prove interesting.…”

Section: Discussionmentioning

confidence: 99%

Generating Efficient Context-Switch Capable Circuits through Autonomous Design Flow

Bourge

Müller

Rousseau

2016

ACM Trans. Reconfigurable Technol. Syst.

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Commercial off-the-shelf (COTS) Field-Programmable Gate Arrays (FPGAs) are becoming increasingly powerful. In addition to their huge hardware resources, they are also integrated into complete systems on chips (SOCs), e.g., in the latest Xilinx Zynq or Altera Stratix platforms. However, cooperation between FPGAs and their surroundings, and the flexibility of hardware task management could still be improved. For instance, mechanisms have yet to be automated to allow multi-user approaches. A reconfigurable resource can be shared between applications or users only if it has a context-switch ability allowing applications to be paused and resumed in response to system demands. Here, we present a high-level synthesis (HLS) design flow producing a context-switch-capable circuit. The design flow manipulates the intermediate representation of an HLS tool to build the context extraction mechanism and to optimize performance for the circuit produced. The method is based on efficient checkpoint selection and insertion of a powerful scan-chain into the initial circuit. This scan-chain can extract flip-flops or memory content. Experiments with the system produced show that it has a low hardware overhead for many benchmark applications, and that the hardware added has a negligible impact on application performance. Comparisons with current standard methods highlight the efficiency of our contributions.

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Section: Discussionmentioning

confidence: 99%

Generating Efficient Context-Switch Capable Circuits through Autonomous Design Flow

Bourge

Müller

Rousseau

2016

ACM Trans. Reconfigurable Technol. Syst.

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“…An RTL scan design makes every register scannable by altering the RTL description [8]. An RTL circuit can be configured in two ways, by using existing multiplexers, and the other utilizing operational units.…”

Section: Multiple Scan Pathsmentioning

confidence: 99%

ASIC Implementation for Multiple Scan at Register Transfer Level

Radzri,

Paraman,

Rusli

2023

J. Phys.: Conf. Ser.

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Design for testability (DFT) is introduced to reduce the complexity of testing integrated circuit and help improve fault coverage. However, conventional DFT with additional 2-to-1 multiplexer (MUX) might add an increasing amount of delay and area overhead. Therefore, register transfer level (RTL) scan design is introduced to overcome this problem. This paper aims to present the development of an ASIC with RTL scan design by using multiple scan paths instead of the conventional technique, which is gate-level (GL) scan insertion to insert scan cells. This method inserts multiple scan cells by utilizing the existing multiplexer and operational units in order to reduce area overhead and delay. Besides, multiple scan paths are implemented instead of a single scan chain to reduce the complexity of the testing process, where a single scan chain has long test application times due to the high number of clock cycles for the scan chain process. RTL design is also modified by adding an extra gate for multiple scan chain insertion. The graph is derived in order to analyse the connection between registers such that the multiple scan paths can be determined accordingly. Synopsys tool is used for synthesized, placement and routing and performing automatic test pattern generation while static timing analysis is used to verify the results of the setup slack time for ASIC design. The simulation result shows that multiple scan paths insertion at RTL level has an area overhead and slack time of about 3.79% and 0.44ns less compared to multiple scan paths insertion at GL for a finite impulse response circuit with comparable high fault coverage and small delay. A comparison of the performance metrics such as area, setup slack time, and fault coverage of the multiple scan chain is done between the RTL scan and GL scan.

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Applying Operations Research to Design for Test Insertion Problems

Kieffer¹,

Zaourar²

2015

Computational Intelligence in Digital and Network Designs and Applications

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A Graph‐Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions

Cited by 4 publications

References 16 publications

Generating Efficient Context-Switch Capable Circuits through Autonomous Design Flow

Generating Efficient Context-Switch Capable Circuits through Autonomous Design Flow

ASIC Implementation for Multiple Scan at Register Transfer Level

Applying Operations Research to Design for Test Insertion Problems

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