A Graph-Based Spatial Mapping Algorithm for a Coarse Grained Reconfigurable Architecture Template

Ma, Lei; Ge, Wei; Qi, Zhi

doi:10.1007/978-3-642-25992-0_89

Cited by 2 publications

(7 citation statements)

References 10 publications

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“…The evaluation of the methodology is twofold. First, we compare our mapping algorithm against the state of the art mapping algorithm presented in [12]. Then, we consider the morphological co-processing unit (MCPU) [1] as a candidate for the use of our mapping methodology, on which we experiment two different applications.…”

Section: Validation and Experimental Resultsmentioning

confidence: 99%

“…We solve this issue using the function Reallocation. The function Reallocation is a modification of the backtracking algorithm presented by Lu et al [12]. The function removes the mapping of the predecessor of the conflicting task, re-add the task and the resource to their respective list and restart the mapping algorithm.…”

Section: Proposed Methodologymentioning

confidence: 99%

“…A considerable amount of approaches brings numerous possibilities for similar mapping problems. Lu et al [12] present a mapping methodology for coarse-grained reconfigurable architectures (CGRA). They use a directed graph as hardware model.…”

Section: Related Workmentioning

confidence: 99%

“…For the evaluation of our approach, we used a modified version of the algorithm presented by Lu et al [12]. We modify the priority list of the resources, used in their work, to comply with the structure of a coarse-grained programmable systolic architecture.…”

Section: First Evaluation and Validationmentioning

confidence: 99%

“…The latter one produces the scheduling based on a list that highlights a significant feature (topological order, task priority) and is commonly used for architectures with a limited number of resources. Many list-based mapping methodologies have been developed [6,8,12,17,22]. Nonetheless, these solutions do not consider the constraint structure of coarse-grained programmable systolic architectures.…”

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confidence: 99%

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A New Mapping Methodology for Coarse-Grained Programmable Systolic Architectures

Barbudo

Dokladalova

Grandpierre

et al. 2019

Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems

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Coarse-grained programmable systolic architectures are designed to meet hard time constraints and provide high-performance computing. They consist of a set of programmable hardware resources with directed interconnections between them. The level of complexity of these architectures limits their re-usability. An automated mapping methodology is required to add a re-usability value to these architectures. In this work, we present a new list-scheduling based mapping methodology for coarse-grained programmable systolic architectures. We use a Directed Acyclic Graph to express the tasks and data dependency of the application as well as the hardware resources organization. We demonstrate that our approach can map different applications, provide a latency estimation and generate the configuration context. This approach could be the base for design space exploration and optimization tools for this family of architectures. CCS CONCEPTS • Theory of computation → Scheduling algorithms; • Hardware → Operations scheduling;

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Section: Validation and Experimental Resultsmentioning

confidence: 99%

Section: Proposed Methodologymentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: First Evaluation and Validationmentioning

confidence: 99%

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confidence: 99%

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