A guiding coverage metric for formal verification

Abstract

Abstract-Considerable effort is made to verify the correct functional behavior of circuits and systems. To guarantee the overall success metric-driven verification flows have been developed. In these flows coverage metrics are omnipresent. Well established coverage metrics for simulation-based verification approaches exist. This is however not the case for formal verification where property checking is a major technique to prove the correctness of the implementation.In this paper we present a guiding coverage metric for this formal verification setting. Our metric reports a single number describing how much of the circuit behavior is uniquely determined by the properties. In addition, the coverage metric guides the verification engineer to achieve completeness by providing helpful information about missing scenarios. This information comes from a new behavior classification algorithm which determines uncovered behavior classes for a signal and allows to compute the coverage of a signal. To measure the complete circuit behavior we devise a coverage metric for a set of signals. The metric is calculated by partitioning the coverage computation into a safe part and an unsafe part where the latter one is weighted accordingly using recursion. This procedure takes into account that in practice properties refer to internal signals which in turn need to be covered them-self. Overall, our metric allows to track the verification progress in property checking and significantly aid the verification engineers in completing the property set.

Inductive Validity Cores

“…Alternately, given two traces that differ only in the value of signal s at a particular time step, if both traces satisfy property P , then s is not covered by P . The work in [77] refines this notion of coverage by providing a numeric score for each incompletely covered signal s. Such metrics are very rigorous but can lead to overspecification: the specification must completely define the input/output function of the implementation.…”

Verifying next generation electronic systems

“…Further reading: [36], [37], [38], [39], [40], [41], [42] Arithmetic: BDD and SAT/SMT techniques suffer from limitations when applied to complex arithmetic, e.g. multipliers.…”