A Hardware Accelerator for the Inference of a Convolutional Neural network

Abstract

<jats:p>Convolutional Neural Networks (CNNs) are becoming increasingly popular in deep learning applications, e.g. image classification, speech recognition, medicine, to name a few. However, the CNN inference is computationally intensive and demanding a large among of memory resources. In this work is proposed a CNN inference hardware accelerator, which was implemented in a co-processing scheme. The aim is to reduce the hardware resources and achieve the better possible throughput. The design was implemented in the Digilent Arty Z7-20 development board, which is based on System on Chip (SoC) Zynq-7000 of Xilinx. Our implementation achieved a of accuracy for the MNIST database using only 12-bits fixed-point format. The results show that the co-processing scheme operating at a conservative speed of 100 MHz can identify around 441 images per second, which is about 17% times faster than a 650 MHz - software implementation. It is difficult to compare our results against other implementations based on Field-Programmable Gate Array (FPGA), because the others implementations are not exactly like ours. However, some comparisons, regarding the logical resources used and accuracy, suggest that our work could be better than previous works.</jats:p>

An Energy-Efficient FPGA-based Convolutional Neural Network Implementation

“…This consumption is taken by Vivado's power report of the implemented design and consisting of 94 mW static and 534 mW dynamic power. This is nearly 67 % lower than the other LeNet CNN architectures which are around 1800 mW [16] [17]. In the experimental setup, the images are loaded using the serial interface of the board and the result is shown on the LEDs of the board.…”

“…In other words, the output of the Python and FPGA designs give exactly the same result in each stage of the CNN. Moreover, for a fair comparison, the proposed accelerator is compared with the other LeNet CNN implementations in the literature having the same number of convolutional and fully connected layers [17] [24] [25]. The design of [24] is using Zynq Ultrascale FPGA and HLS is used in the development stage.…”

“…These engines make the convolution operation in a pipelined manner. There are also works using the Zynq series FPGAs, and these works process the data with the help of embedded processor and programmable logic together in the accelerator [16], [17]. Lenet, Alexnet and VGGNet are the most popular CNNs used in the FPGA implementation.…”

Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration

“…Various CNN implementations on FPGA have been reported in literature [11]- [13], focusing on different aspects, e.g., the optimization of only the convolutional layers [14], [15] or the overall accelerator throughput [16]. There are also SW/HW co-design solutions that exploit the aggregate power of both an embedded processor and the programmable logic [17], [18]. Some [19], [20] present resource-intensive designs and achieve high throughput disregarding power consumption, while others implement binary neural networks (BNNs) that achieve high power efficiency at the cost of reduced accuracy using binary weights/biases [21].…”

Special Issue in Artificial Intelligence

“…AI applications include prediction, recommendation, classification and recognition, object detection, natural language processing, autonomous systems, among others. The topics of the articles in this special issue include deep learning applied to medicine [1,3], support vector machines applied to ecosystems [2], human-robot interaction [4], clustering in the identification of anomalous patterns in communication networks [5], expert systems for the simulation of natural disaster scenarios [6], real-time algorithms of artificial intelligence [7], and big data analytics for natural disasters [8].…”