A hardware algorithm for fast logarithmic computation with exponential convergence rate

Chen, Chichyang; Chen, Rui‐Lin; Sheu, Ming‐Hwa

doi:10.1080/02533839.2005.9671043

Cited by 4 publications

(7 citation statements)

References 4 publications

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“…However, its convergence rate is still linear. This problem has been overcome by our previous work in [6]. The convergence rate of our previous work [6] is exponential and the number of convergence stages is ⎡ ⎤…”

Section: Introductionmentioning

confidence: 98%

“…Digit-pipelining can not be applied in the architecture design for the improvement of the system throughput. In this research, a digit on-line logarithmic algorithm is proposed to improve the system throughput of the logarithmic algorithm proposed in [6]. The convergence rate is the same as that of the algorithm in [6].…”

Section: Introductionmentioning

confidence: 99%

“…In this research, a digit on-line logarithmic algorithm is proposed to improve the system throughput of the logarithmic algorithm proposed in [6]. The convergence rate is the same as that of the algorithm in [6]. However, the first partial logarithmic result can be computed after only some leading digits of the operand are available.…”

Section: Introductionmentioning

confidence: 99%

“…The proposed digit on-line algorithm for logarithmic computation with exponential convergence rate is modified from the method used in [6]. The number of recurrence stages is reduced in [6] by using the adoption of the quadratic divideby reciprocal algorithm [5].…”

Section: Introductionmentioning

confidence: 99%

“…The number of recurrence stages is reduced in [6] by using the adoption of the quadratic divideby reciprocal algorithm [5]. It is used to derive the reciprocal of the divisor.…”

Section: Introductionmentioning

confidence: 99%

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A hardware algorithm for fast digit on-line logarithmic computation with exponential convergence rate

Chen

2009

2009 6th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technolog

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In this research, a hardware algorithm for digit online logarithmic computation is proposed. This algorithm is based on a fast digit-parallel logarithmic algorithm that was proposed previously. The drawback of the previous algorithm is that the computation cannot be digit pipelined with other computations. Our new algorithm will generate the partial logarithmic result after only some input digits of the operand are available. Thus, the high throughput of the computing system can be attained with the use of digit pipelining in the design of the hardware architecture. Furthermore, the latency of the pipeline is short because the convergence rate of the algorithm is exponential. For example, when the word length of the operand is 24, the number of pipeline stages is only four. Base on our proposed digit on-line method, we have designed the architecture of a 24-bit logarithmic unit. The exhausted test of the 24-bit unit shows that our algorithm and error analysis are correct.Index: Multiplicative normalization, logarithmic computation, digit on-line algorithm, digit pipeline architecture, logarithmic number system.

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Section: Introductionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…The number of recurrence stages is reduced in [6] by using the adoption of the quadratic divideby reciprocal algorithm [5]. It is used to derive the reciprocal of the divisor.…”

Section: Introductionmentioning

confidence: 99%

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A hardware algorithm for fast digit on-line logarithmic computation with exponential convergence rate

Chen

2009

2009 6th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technolog

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Error analysis of LNS addition/subtraction with direct-computation implementation

Chen

2009

IET Comput. Digit. Tech.

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Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor

Chen

Chow

2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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LNS (logarithmic number system) arithmetic has the advantages of high-precision and high performance in complex function computation. However, the large hardware problem in LNS addition/subtraction computation has made the large word-length LNS arithmetic implementation impractical. In this research, we proposed a hybrid floating-point (FLP)/LNS processor that can utilize the FLP multiplication-addition-fused (MAF) unit and the FLP division unit for implementing the computation of LNS addition/subtraction. With unified representation format in FLP and LNS numbers, this hybrid processor is versatile because it can execute the FLP-to-LNS and LNS-to-FLP conversions easily, without any extra hardware cost, in addition to the FLP multiplication-addition/subtraction, FLP division, and LNS addition/subtraction instructions. It is cost-effective because the FLP hardware is shared by the LNS unit. A 32-bit hybrid FLP/LNS processor is implemented on the Xilinx Virtex II multimedia FF896 development board. From the synthesis results, the hardware of the 32-bit hybrid processor is at most three times that of a 32-bit pure FLP processor. Our proposed hybrid FLP/LNS approach has made the design of very large wordlength LNS arithmetic processors become practical.

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A hardware algorithm for fast logarithmic computation with exponential convergence rate

Cited by 4 publications

References 4 publications

A hardware algorithm for fast digit on-line logarithmic computation with exponential convergence rate

A hardware algorithm for fast digit on-line logarithmic computation with exponential convergence rate

Error analysis of LNS addition/subtraction with direct-computation implementation

Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor

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