2022
DOI: 10.1007/978-3-030-96498-6_12
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A Hardware Co-design Workflow for Scientific Instruments at the Edge

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Cited by 2 publications
(2 citation statements)
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“…The reduction stage takes the output of multiple parallel encoders, consisting of both constant and variable-length data and turns it into a single continuous variable-length output. The implementation and resource optimization strategy is described in our previous work [34]. The packing module then combines this variable-length data across clock cycles until a fixed number of bits has accumulated.…”
Section: Coalescing Modulesmentioning
confidence: 99%
“…The reduction stage takes the output of multiple parallel encoders, consisting of both constant and variable-length data and turns it into a single continuous variable-length output. The implementation and resource optimization strategy is described in our previous work [34]. The packing module then combines this variable-length data across clock cycles until a fixed number of bits has accumulated.…”
Section: Coalescing Modulesmentioning
confidence: 99%
“…Our proposed solution is realized by means of hardware specialization and can also be an essential component in other specialized hardware designs if we provide our design as a reusable hardware library. In our recent study [11], we discussed the importance of streaming computing at the edge of scientific instruments along with the challenges and opportunities within hardware specialization methodology. This included several usage examples of opensource hardware design tools such as Chisel and Yosys [12].…”
Section: Introductionmentioning
confidence: 99%