A hardware mechanism to reduce the energy consumption of the register file of in-order architectures

Abstract

This paper introduces an efficient hardware approach to reduce the register file energy consumption by turning unused registers into a low power state. Bypassing the register fields of the fetch instruction to the decode stage allows the identification of registers required by the current instruction (instruction predecode) and allows the control logic to turn them back on. They are put into the low-power state after the instruction use. This technique achieves an 85% energy reduction with no performance penalty.Keywords: register file; in-order; power reduction; predecode; hardware approach.

On consumption shifting scheme for power

“…As technology evolves, power has been widely used in both human's life and study (Ayala et al, 2008;Yan et al, 2008). With the increasing demand for electricity, then the task to keep it precisely balanced with supply becomes especially challenging (Fang et al, 2012).…”