A hardware pyramid vector quantizer

Abstract

A single-chip, dedicated processor for implementation of pyramid vector quantization is present.ed. The computational requirements of she vect,or quantizer encoding algorith~n are described. and a processor architecture and inst,ruction set selected for efficient imple~nentation of the vec.tor quantizat.ion. The processor performance is characterized by analysis and si~nulation.with a general conclusion that for a st,at.e---of-the -art VLSI inl-ple~nentation. 64-dimensional vectors can he vector quantized at a sample rate of 16 kHz.Vector quantization. or block source encoding, has heconie of increased interest and importance in d a h compression applications during the past ten years. There are t.wo principal approaches to vector quantizer (VQ) design; namely, the ciustering algorithm of Linde. Buzo. and Gray [lj, and the use of lattices, as pioneered hy Gersho 21, Conway and Sloane i3-61, and Sayood, Gibson, and Rost [i:,. The clustering algorithm approach t.o VQ design is presently enjoying great popularity in VQ-based source coding research (see [8?9] and the references therein). This algorithn~ is easily