A Hardware Task Scheduler for Embedded Video Processing

Alkadi, G.; Terechko, Andrei

doi:10.1007/978-3-540-92990-1_12

Cited by 31 publications

(21 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The TriMedia-based multi-core system contains a centralized task scheduling unit based on Carbon. TMU is a look-ahead task management unit for reducing the task retrieval latency that accelerates task creation and synchronization similar to video-oriented task schedulers [9].…”

Section: Related Workmentioning

confidence: 99%

Picos: A hardware runtime architecture support for OmpSs

Yazdanpanah

Álvarez

Jiménez-González

et al. 2015

Future Generation Computer Systems

View full text Add to dashboard Cite

OmpSs is a programming model that provides a simple and powerful way of annotating sequential programs to exploit heterogeneity and task parallelism based on runtime data dependency analysis, dataflow scheduling and out-of-order task execution; it has greatly influenced Version 4.0 of the OpenMP standard. The current implementation of OmpSs achieves those capabilities with a puresoftware runtime library: Nanos++. Therefore, although powerful and easy to use, the performance benefits of exploiting finegrained (pico) task parallelism are limited by the software runtime overheads. To overcome this handicap we propose Picos, an implementation of the Task Superscalar (TSS) architecture that provides hardware support to the OmpSs programming model. Picos is a novel hardware dataflow-based task scheduler that dynamically analyses inter-task dependencies and identifies task-level parallelism at run-time. In this paper, we describe the Picos Hardware Design and the latencies of the main functionality of its components, based on the synthesis of their VHDL design. We have implemented a full cycle-accurate simulator based on those latencies to perform a design exploration of the characteristics and number of its components in a reasonable amount of time.Finally, we present a comparison of the Picos and Nanos++ runtime performance scalability with a set of real benchmarks. With Picos, a programmer can achieve ideal scalability using aggressive parallel strategies with a large number of fine granularity tasks.

show abstract

Section: Related Workmentioning

confidence: 99%

Picos: A hardware runtime architecture support for OmpSs

Yazdanpanah

Álvarez

Jiménez-González

et al. 2015

Future Generation Computer Systems

View full text Add to dashboard Cite

show abstract

“…For example, Carbon [12] assumes independent tasks and uses hardware queues to retrieve tasks with low latency. An example of a hardware accelerator that targets a certain application domain is the hardware task scheduler optimized for H.264 decoding [13]. It only supports a specific dependency pattern, and any modification to the task structure of the application would lead to incompatibility.…”

Section: B Hardware Task Managementmentioning

confidence: 99%

An Integrated Hardware-Software Approach to Task Graph Management

Engelhardt

Dallou

Elhossini

et al. 2014

2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security

View full text Add to dashboard Cite

Abstract-Task-based parallel programming models with explicit data dependencies, such as OmpSs, are gaining popularity, due to the ease of describing parallel algorithms with complex and irregular dependency patterns. These advantages, however, come at a steep cost of runtime overhead incurred by dynamic dependency resolution. Hardware support for task management has been proposed in previous work as a possible solution. We present VSs, a runtime library for the OmpSs programming model that integrates the Nexus++ hardware task manager, and evaluate the performance of the VSs-Nexus++ system. Experimental results show that applications with fine-grain tasks can achieve speedups of up to 3.4×, while applications optimized for current runtimes attain 1.3×. Providing support for hardware task managers in runtime libraries is therefore a viable approach to improve the performance of OmpSs applications.

show abstract

“…In the same context, related work proposes application-specific hardware task schedulers [15]. Our work explores general-purpose hardware primitives, with several potential uses, and compares them in alternative implementations of a software stack for high-level parallel programming.…”

Section: Related Workmentioning

confidence: 99%

Fine-grain OpenMP runtime support with explicit communication hardware primitives

Tendulkar

Papaefstathiou

Nikiforos

et al. 2011

2011 Design, Automation &Amp; Test in Europe

View full text Add to dashboard Cite

Abstract-We present a runtime system that uses the explicit on-chip communication mechanisms of the SARC multi-core architecture, to implement efficiently the OpenMP programming model and enable the exploitation of fine-grain parallelism in OpenMP programs. We explore the design space of implementation of OpenMP directives and runtime intrinsics, using a family of hardware primitives; remote stores, remote DMAs, hardware counters and hardware event queues with automatic responses, to support static and dynamic scheduling and data transfers in local memories. Using an FPGA prototype with four cores, we achieve OpenMP task creation latencies of 30-35 processor clock cycles, initiation of parallel contexts in 50 cycles and synchronization primitives in 65-210 cycles.

show abstract

A Hardware Task Scheduler for Embedded Video Processing

Cited by 31 publications

References 11 publications

Picos: A hardware runtime architecture support for OmpSs

Picos: A hardware runtime architecture support for OmpSs

An Integrated Hardware-Software Approach to Task Graph Management

Fine-grain OpenMP runtime support with explicit communication hardware primitives

Contact Info

Product

Resources

About