A hardware virtual machine for networked reconfiguration

UML 2.0 provides a rich set of diagrams for systems documentation and specification. Many efforts have been undertaken to employ different aspects of UML for multiple domains, mainly in the area of software systems. Considering the area of electronic design automation, however, we currently see only very few approaches, which investigate UML for hardware design and hardware/software co-design. In this article, we present an approach for executable UML closing the gap from system specification to its model-based execution on reconfigurable hardware. For this purpose, we present our Abstract Execution Platform (AEP), which is based on a Virtual Machine running an executable UML subset for embedded software and reconfigurable hardware. This subset combines UML 2.0 Class, StateMachine and Sequence Diagrams for complete system specification. We describe how these binary encoded UML specifications can be directly executed and give the implementation of such a virtual machine on a Virtex II FPGA. Finally, we present evaluation results comparing the AEP implementation with C code on a C167 microcontroller.

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On Virtualization of Reconfigurable Hardware in Distributed Systems

Nadeem

Wong

2012

2012 41st International Conference on Parallel Processing Workshops

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A hardware virtual machine for networked reconfiguration

Cited by 5 publications

References 3 publications

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A Model-Based Approach for Executable Specifications on Reconfigurable Hardware

On Virtualization of Reconfigurable Hardware in Distributed Systems

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