A HDL based reduced area NOC router architecture

Suraj, M. S.; Muralidharan, D.; Kumar, K. Seshu

doi:10.1109/icevent.2013.6496593

Cited by 4 publications

(3 citation statements)

References 5 publications

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“…They showed that multiplexer type crossbar gives better efficiency than matrix type in terms of area and power. A low area router architecture for NoCs based on HDL was proposed in [53]. Here it uses two crossbar switches instead of one.…”

Section: Areamentioning

confidence: 99%

A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level

Manzoor

Mir

Hakim

2021

SCPE

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As the trend of technology shrinking continues a vast amount of processors are being incorporated in a limited space. Due to this almost half of the chip area in Multi-Processor Systems-on-Chips (MPSoCs) is under interconnections, which pose a big problem for communication. Network-on-Chips (NoCs) evolved as a significant scalable solution for removing wiring congestion and communication problem in MPSoCs. NoCs provide the advantage of customized architecture, increased scalability and bandwidth. NoC is a structured framework where communication is the prime concern. In this review paper we present an overview of research and design approaches in the communication centric areas of NoCs. Here we have tried to discuss and iterate most of the available work done for communication in 2D NoCs. This paper gives the insight of different attributes and performance parameters of NoCs. Further it gives a detailed description of how topology, flow control and routing mechanisms can affect the qualitative aspects (performance) of NoCs. It then explains how various attributes of routing can help in increasing the efficacy of NoCs. Subsequently a brief review of different simulators used for NoCs is given. All of this is provided based on the survey of academic, theoretical and experimental approaches presented in the past. Finally some suggestions for future work are also given.

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Section: Areamentioning

confidence: 99%

A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level

Manzoor

Mir

Hakim

2021

SCPE

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“…The most popular XY routing algorithm [19] is proposed by Wang Zhang and Ligang Hou in 2009. Based on literature [21], this study considered XY routing algorithm with 2×2 Mesh topology consisting of 4 nodes to validate data transfer as shown in Figure 2. The source and destination router node have to be identified before the transfer of data.…”

Section: 2xy Routing Algorithm For 2×2 Networkmentioning

confidence: 99%

An efficient FPGA based NoC architecture for data communication

Jamagoud¹,

Bhairannawar²

2018

IJACR

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NoC is a new model in which a single silicon chip is utilized to execute various communication features used in substantial to huge scale integration systems. NoC is another change to the universe of systems and also the other way to deal with disadvantages like wiring delay. There are numerous types of interconnections like point-to-point, bus architecture, carbon nanotubes, optical fiber [1] where NoC perform is better to reduce the interconnection issues in future designs. System on chips designed using NoCs are getting popular in these days which provide solutions to the problem related to bus based designs and considered as the future of the application specific integrated circuit (ASIC) design [2]. NoC basically has three building blocks router, links and network adapter (NA) [3]. NoC approach has numerous benefits over traditional bus method and also provides high throughput as buses are less scalable and limited bandwidth [4].

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“…They also present a new router architecture called Flexible, Extensible Router NoC (FeRoNoc). The NoC router architecture with five port presented in [10], which utilizes dual crossbar arrangement. Due to which latency arises, this reduces using predominant routing algorithm.…”

Section: Introductionmentioning

confidence: 99%

Network on Chip Router Architecture Performance Analysis by using VHDL

Chandravanshi¹,

Tiwari²

2016

IJCA

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Networks-on-Chip (NoCs) are increasingly used in many-core architectures. Todays technology for ASICs supports Networks-on-Chip designs which can have 100 million gates on a single chip. In order to implement a competitive NoC architecture in FP-GAs, the area occupied by the network should be kept to a minimum. This helps in utilizing maximum area by the logic while maintaining the performance of the router network. Reducing area also reduces the power consumption. NOC's designs promise to offer considerable advantages over the traditional bus-based designs, in solving the numerous technological, economic and productivity problems associated with billion-transistor system-on-chip development. Here, a very flexible network is designed to propose a highly scalable and can be easily changed to accommodate various needs. This proposed work focused on implementation, analysis and verification of a five port routers. The building blocks of the router are input/output, multiplexer/demultiplexer, crossbar switch, buffer register and arbiters. The arbiters uses the round robin algorithm. The proposed NOC architecture is simulated in Xilinx ISE10.1 software. The source code is written in VHDL. This design is suitable for building networks with irregular topologies and with low latency and high throughput.

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A HDL based reduced area NOC router architecture

Cited by 4 publications

References 5 publications

A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level

A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level

An efficient FPGA based NoC architecture for data communication

Network on Chip Router Architecture Performance Analysis by using VHDL

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