A Heuristic Algorithm for Deriving Compact Models of Processor Instruction Sets

Abstract

Finding a compact formal representation of a processor instruction set is important for easier comprehension by the designer, as well as for synthesis of an efficient hardware implementation of the processor's microcontroller.We present a new heuristic algorithm for deriving compact models of processor instruction sets. The algorithm is based on finding similarities between pairs of instructions and assigning similar opcodes (using a Hamming distance metric) to similar instructions (using a newly introduced instruction similarity metric). We demonstrate that this heuristic produces results with an average overhead, in terms of area, of 7.8% in comparison to the global optimum on the benchmarks we studied (subsets of instructions of ARM Cortex M0+, Texas Instruments MSP430 and Intel 8051 processors).The algorithm is implemented as an open-source plugin for the Workcraft framework and is validated on a case study of a subset of 61 (out of 68) instructions of ARM Cortex M0+ processor. We compare the presented algorithm against a number of other available implementations.

Mining Conditional Partial Order Graphs from Event Logs

“…Our experiments have shown that only heuristic CPOG synthesis [22] can cope with event logs of realistic sizes. Other, more sophisticated encoding methods are not scalable enough.…”

“…A more sophisticated approach, which produces CPOGs with more complex conditions has been proposed in [21], however, it has poor scalability and cannot be applied to large process mining instances. The most scalable approach to date, as confirmed by the experiments in §7.3, has been developed in [22] and is based on simulated annealing. All encoding methods are supported by open-source modelling framework Workcraft [7], which we used in our experiments.…”

“…Scenco is a collection of CPOG synthesis algorithms that have been developed in a series of publications and integrated in Workcraft: graph colouring based single literal synthesis [4], SAT-based synthesis [21], and heuristic synthesis [22]. We use Scenco for encoding collections of partial orders produced by PGminer.…”

Efficient composition of scenario‐based hardware specifications

“…7), the function heuristicEncoding handles the output of the previous function enc and advances to enc best through a sequence of swap moves that inspects many intermediate encodings enc next . Given a correct enc (see line 2), each intermediate encoding enc next derived by a swap (see lines [7][8][9][10][11][12] is always an encoding with no conflicting codes (i.e. code swap does not introduce encoding conflicts).…”

“…We discuss achieved results and future research in Section 7. This study is an extended version of [11] and includes the following changes. We review the CPOG-based design methodology in Section 2.2 and summarise differences with other existing behavioural synthesis approaches in Section 3.1.…”