A heuristic algorithm for reducing system-level test vectors with high branch coverage

Abstract

We introduce a heuristic that generates as few a number of test vectors as possible with high branch coverage for the functional verification of digital design. The challenge is how to save time and effort for sufficient verification at system-level. We focus on generating test vectors from the circuit specification written in C. We reuse them to SystemC description by removing their redundancies while maintaining the branch coverage as is. Experimental results of our practical design show that over 90% on average of the redundant test vectors were reduced with 100% branch coverage maintained. The reused test vectors for SystemC Bus Cycle Accurate models scored 80% branch coverage on average. These results are significant for saving verification cost and beneficial for simplifying debugging works.