A Heuristic Boolean NPN Equivalent Matching Verification Method Based on Shannon Decomposition

Abstract

In this paper, we describe a new verification method to accelerate the input negation and/or input permutation and/or output negation (NPN) Boolean matching for a single-output completely specified Boolean function. Through research on the Boolean Shannon decomposition binary tree, we prove that the signature vectors of the left child node and right child node are complementary relative to the signature vector of the parent node. We introduce an independent variable check to speed up the detection of candidate transformation. The proposed approach utilises this complementarity, a symmetry check, an independent variable check and a phase collision check, which can quickly verify whether the candidate transformation obtained in the detection of the candidate transformation of the Boolean matching process is accurate. We perform experiments on two types of Boolean function sets. One type consists of Boolean functions from randomly generated circuits. The other is exported from the Microelectronics Center of North Carolina (MCNC) benchmark. The experimental results show that the average runtime of our algorithm is 68.8% faster than those in on two randomly generated circuits and 51% faster than those in when tested on the MCNC benchmark circuit set. Therefore, the experimental results demonstrate the effectiveness of the proposed method.INDEX TERMS Boolean matching, NPN equivalence, Shannon expansion, Shannon decomposition binary tree, signature vector.

A new scheme of all-optical 2:1 multiplexer (MUX) and MUX-based combinational circuits using nonlinear kerr-type materials

“…In 2020, Dalai Gowri Sankar Rao et al presented all-wavelengths, high bandwidth, and immunity to electromagnetic interference contribute to the development of compact, lightweight devices, fostering the integration of high-speed communication technologies [61][62][63][64][65]. In this research, we introduce novelty by applying the Shannon Decomposition (SD) theorem [66,67] to construct all-optical (AO) logic gates, including NOT, OR, AND, NAND, NOR, etc, exclusively from an AO 2:1 multiplexer (MUX). Utilizing the AO Shannon-based MUX allows the generation of various Boolean functions with minimal AO MUX units, contributing to cost-effective computing.…”