A Heuristic (delta, D) Digraph to Interpolate between Hypercube and de Bruijn Topologies for Future On-Chip Interconnection Networks

Abstract

The paper presents as background several graphs referred to (delta, D) digraphs including the Hypercube and de Bruijn. It shows the major disadvantages when implementing these topologies on chip interconnection networks. Then, the paper presents the "Small-World Heuristic" (SWH), which aims to find a network topology for a large number of nodes that has a maximum out degree and a small diameter, while maintaining an acceptable level of connectivity. It is proposed that this heuristic can be used to determine a compromise between Hypercube and de Bruijn when implementing networks on FPGA or in VLSI.

Moore Graphs and Beyond: A survey of the Degree/Diameter Problem

“…This trend is not confined only to graph theorists. Indeed, since 2005, we have found many new references in computer science, in particular, parallel and distributed processing [112], [113], [130], [235], optical networks [88], interconnection networks [345], [346], [315], [354], [193], [214], [219], P2P networks [194], [195], [234], [197], [198], [281], [295], etc.…”