A heuristic for constructing a rectilinear Steiner tree by reusing routing resources over obstacles

Zhang, Hao; Dong-yi, YE; Guo, Wenzhong

doi:10.1016/j.vlsi.2016.06.001

Cited by 16 publications

(4 citation statements)

References 27 publications

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“…Liu et al (2014a) proposed a multi-layer obstacle avoidance RSMT construction method based on geometric reduction method (Liu et al, 2014a). Zhang, Ye & Guo (2016) proposed a heuristic for constructing a RSMT with slew constraints to maximize routing resources over obstacles (Zhang, Ye & Guo, 2016). Teig (2002) adopted XSMT, which is superior to RSMT in terms of average wire length optimization (Teig, 2002).…”

Section: Research Status Of Rsmt and Xsmtmentioning

confidence: 99%

X-architecture Steiner minimal tree algorithm based on multi-strategy optimization discrete differential evolution

Liu

Yang

et al. 2021

PeerJ Computer Science

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Global routing is an important link in very large scale integration (VLSI) design. As the best model of global routing, X-architecture Steiner minimal tree (XSMT) has a good performance in wire length optimization. XSMT belongs to non-Manhattan structural model, and its construction process cannot be completed in polynomial time, so the generation of XSMT is an NP hard problem. In this paper, an X-architecture Steiner minimal tree algorithm based on multi-strategy optimization discrete differential evolution (XSMT-MoDDE) is proposed. Firstly, an effective encoding strategy, a fitness function of XSMT, and an initialization strategy of population are proposed to record the structure of XSMT, evaluate the cost of XSMT and obtain better initial particles, respectively. Secondly, elite selection and cloning strategy, multiple mutation strategies, and adaptive learning factor strategy are presented to improve the search process of discrete differential evolution algorithm. Thirdly, an effective refining strategy is proposed to further improve the quality of the final Steiner tree. Finally, the results of the comparative experiments prove that XSMT-MoDDE can get the shortest wire length so far, and achieve a better optimization degree in the larger-scale problem.

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Section: Research Status Of Rsmt and Xsmtmentioning

confidence: 99%

X-architecture Steiner minimal tree algorithm based on multi-strategy optimization discrete differential evolution

Liu

Yang

et al. 2021

PeerJ Computer Science

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“…Zhang et al [75] proposed a heuristic algorithm that constructs an extended rectilinear Steiner tree grid as a routing graph, ensuring that the routing graph contains at least one optimal solution for RSMT problem and one near optimal solution OARSMT problem. And by modifying the shortest path heuristic algorithm, a step-growth heuristic algorithm is designed to solve the constrained SMT problem.…”

Section: Lrsmtmentioning

confidence: 99%

A Survey on Steiner Tree Construction and Global Routing for VLSI Design

et al. 2020

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Global Routing (GR) is a crucial and complex stage in the Very Large-Scale Integration (VLSI) design, which minimizes interconnect wirelength and delay to optimize the overall chip performance. Steiner tree construction is one of the basic models of VLSI physical design, which is usually used in the initial topology creation for noncritical nets in physical design. In a GR process, a Steiner Minimum Tree (SMT) algorithm can be invoked millions of times, which means that SMT algorithm has great significance for the final quality of GR. Some of the research works are surveyed in this paper to understand GR and SMT problems and to learn the available solutions. Firstly, we systematically dissect three types of subproblems in Steiner tree construction and three types of GR methods. Then, we investigate the recent progress under two new technology models. Finally, the survey concludes with a summary of possible future research directions.

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“…The exiting Elmore model induces higher error for slew calculation. To overcome this model incorporates slew calculation presented in [12] in to our model. The proposed model addresses the slew constraint for routing on top of obstacle and improves performance in term of worst negative slack.…”

Section: The Contribution Of Work Can Be Classified As Followsmentioning

confidence: 99%

Obstacle aware delay optimized rectilinear steiner minimum tree routing

Guruvare¹,

Prasad²

2019

IJEECS

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This work presents a method to solve the problem of constructing Rectilinear Steiner Minimum Tree (RSMT) for a group of pins in the presence of obstacles. In modern very large-scale integrated circuit (VLSI) designs, the obstacles, generally blocks the metal and the device layer. Therefore routing on top of blockage is a possible solution but buffers cannot be placed over the obstacle. Modern VLSI design OARSMT construction has long wire length, which results in signal violation. To address this issue a slew constraint interconnect need to be considered in routing over obstacle. This is called the Obstacle-Avoiding Rectilinear Steiner minimum trees (OARSMT) problem with slew constraints over obstacles. The drawback of traditional OARSMT is that they only consider slew constraint, and delay constraints are neglected. It induces high routing resources overhead due to buffer insertion and does not solve global routing solution. This work presents an Obstacle Aware Delay Optimized Rectilinear Steiner Minimum Tree (OADORSMT) Routing to address the delay, slew constraint and reduce the routing resources. Experiments are conduced to evaluate the performance of proposed approach over existing approach in term of wire length and worst negative slack. The experiments are conducted for small and large nets considering fixed and varied obstacles and outcome shows the proposed efficiency over existing approaches. The OADORSMT is designed in such a way where it can be parallelized to obtain better efficiency.

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A heuristic for constructing a rectilinear Steiner tree by reusing routing resources over obstacles

Cited by 16 publications

References 27 publications

X-architecture Steiner minimal tree algorithm based on multi-strategy optimization discrete differential evolution

X-architecture Steiner minimal tree algorithm based on multi-strategy optimization discrete differential evolution

A Survey on Steiner Tree Construction and Global Routing for VLSI Design

Obstacle aware delay optimized rectilinear steiner minimum tree routing

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