A Hf0.5Zr0.5O2 ferroelectric capacitor-based half-destructive read scheme for computing-in-memory

Zhao, Yulin; Wang, Yuan; Zhang, Donglin; Han, Zhongze; Hu, Qiao; Liu, Xuanzhi; Ding, Qingting; Cheng, Jinhui; Zhang, Wenjun; Cao, Yue; Zhou, Ruixi; Luo, Qing; Yang, Jianguo; Lv, Hangbing

doi:10.1007/s11432-021-3490-3

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“…However, the scaling of FeRAM capacitors is still limited compared to that of transistors, leading to low area efficiency. For instance, the ferroelectric capacitor (FeCAP) area was 40 × 10 3 nm 2 for the 28 nm node in Stefan et al's work [8], and the FeRAM area was 0.49 um 2 for the 130 nm node in Zhao et al's work [9]. Considering the above reasons, multi-level cell (MLC) FeRAM for high-density storage applications has also been continuously explored in recent studies.…”

Section: Introductionmentioning

confidence: 99%

Design and Simulation Analysis of a 3TnC MLC FeRAM Using a Nondestructive Readout and Offset-Canceled Sense Amplifier for High-Density Storage Applications

et al. 2023

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Hf0.5Zr0.5O2-based multi-level cell (MLC) ferroelectric random-access memory (FeRAM) has great potential for high-density storage applications. However, it is usually limited by the issues of a small operation margin and a large input offset. The study of circuit design and optimization for MLC FeRAM is necessary to solve these problems. In this work, we propose and simulate a configuration for a Hf0.5Zr0.5O2-based 3TnC MLC FeRAM macro circuit, which also presents a high area efficiency of 12F2 for each bit. Eight polarization states can be distinguished in a single fabricated Hf0.5Zr0.5O2-based memory device for potential MLC application, which is also simulated by a SPICE model for the subsequent circuit design. Therein, a nondestructive readout approach is adopted to expand the reading margin to 450 mV between adjacent storage levels, while a capacitorless offset-canceled sense amplifier (SA) is designed to reduce the offset voltage to 20 mV, which improves the readout reliability of multi-level states. Finally, a 4 Mb MLC FeRAM macro is simulated and verified using a GSMC 130 nm CMOS process. This study provides the foundation of circuit design for the practical fabrication of a Hf0.5Zr0.5O2-based MLC FeRAM chip in the future, which also suggests its potential for high-density storage applications.

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Section: Introductionmentioning

confidence: 99%