A hierarchical parallel evolvable hardware based on network on chip

Abstract

Evolvable Hardware (EHW) is inspired by natural evolution for the automatic design of hardware systems, based on Evolutionary Algorithm (EA). This paper proposed a novel optimization process of evolution system by utilizing a two-level hierarchical parallel algorithm and constructing EHW system into NoC infrastructure. The NoC is specially designed for high-speed reconfigurable hardware. Experimental results show that the usage of the hierarchical parallel algorithm can achieve 188.7% and 675.7% improvement in convergence speed against the global parallel one or the serial one; moreover, by using the NoC architecture, the Single Evolution Cycle Run Time can be at least two orders of magnitude faster than the state-of-the-art EHW systems when evolving the same scale of circuits.