Proceedings of IEEE International Electron Devices Meeting
DOI: 10.1109/iedm.1993.347408
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A high capacitive-coupling ratio (HiCR) cell for 3 V-only 64 Mbit and future flash memories

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Cited by 17 publications
(6 citation statements)
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“…HiCR cells were first presented in 1993 for 3-V-only 64-Mb Flash memories [81]. They are contactless cells with a high capacitive coupling ratio, programmed and erased by FN tunneling.…”
Section: G High Capacitive Coupling Ratiomentioning
confidence: 99%
“…HiCR cells were first presented in 1993 for 3-V-only 64-Mb Flash memories [81]. They are contactless cells with a high capacitive coupling ratio, programmed and erased by FN tunneling.…”
Section: G High Capacitive Coupling Ratiomentioning
confidence: 99%
“…The electric potential of the ferro‐floating layer is carried by the gate voltage, which is scaled by the capacitance‐coupling ratio ( γ = C (blk+ff) /( C (blk+ff) + C tun )) when the charges are absent from the ferro‐floating layer. Here, C (blk+ff) is the series capacitance of the blocking and ferro‐floating layers, and C tun is the capacitance of the tunneling layer 52 . In the ferro‐floating memory, the injected charges by the tunneling mechanism and the polarization charges by the ferroelectric switching mechanism exist in the ferro‐floating layer.…”
Section: Resultsmentioning
confidence: 99%
“…Here, C (blk+ff) is the series capacitance of the blocking and ferro-floating layers, and C tun is the capacitance of the tunneling layer. 52 In the ferro-floating memory, the injected charges by the tunneling mechanism and the polarization charges by the ferroelectric switching mechanism exist in the ferro-floating layer. Therefore, the electric potential is modified by (Q store + Q ferro )/(C (blk+ff) + C tun ), where Q store is the stored charge in the ferro-floating layer and Q ferro is the polarization charge in the channel side of the ferro-floating layer.…”
Section: Device Scheme and Operation Of The Vdw-based Ferro-floating ...mentioning
confidence: 99%
“…In the conventional concept, the floating gate voltage is determined by the control gate voltage through a coupling ratio of γ=C ono /(C ono +C tun ) [7], where C ono is the control gate to floating gate capacitance and C tun is the tunnel oxide capacitance. As the design rule of NAND flash memory is scaled down, it is hard to ignore its parasitic effects on cell operation cell.…”
Section: Resultsmentioning
confidence: 99%