2001
DOI: 10.1109/77.919530
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A high density 4 kA/cm/sup 2/ Nb integrated circuit process

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Cited by 28 publications
(14 citation statements)
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“…The circuit was fabricated in TRW's standard 4 kA/cm Nb IC process [9], [10]. In test, signals traversed two differentialcoupled circuits; the first went from chip ground to a floating ground island and the second went from the island back to chip ground.…”
Section: B Testmentioning
confidence: 99%
See 1 more Smart Citation
“…The circuit was fabricated in TRW's standard 4 kA/cm Nb IC process [9], [10]. In test, signals traversed two differentialcoupled circuits; the first went from chip ground to a floating ground island and the second went from the island back to chip ground.…”
Section: B Testmentioning
confidence: 99%
“…According to TRW's standard process [9], [10], the capacitors are formed by anodization of the ground plane. The junction base electrode then forms the upper capacitor electrode.…”
Section: A Designmentioning
confidence: 99%
“…Both the integrated circuit ͑IC͒ chip and the carrier were fabricated at TRW according to standard Nb processes, 14,15 except that the junction critical current density was doubled to 8 kA/cm 2 . The circuit conforms to rather modest design rules that have a 1.25 m minimum Josephson junction diameter.…”
Section: High Speed Data Link Between Digital Superconductor Chipsmentioning
confidence: 99%
“…1 ' 2 Circuit-level computer-aided design (CAD) and testing tools have been developed to cope with challenges of practical low & medium-scale RSFQ chip design and testing. 3,4 ' 5 ' 6 A new 4 kA/cm 2 , 1.75-^m Nb/AlOx/Nb Josephson junction technology developed by TRW, Inc. 7 has allowed reproducible fabrication of relatively large chips containing tens of thousands junctions with tolerable variations of their technological parameters. The final contribution has come from the architectural and design studies of the SPELL RSFQ processors for a petaflops-scale system within the HTMT project.…”
Section: Introductionmentioning
confidence: 99%