A 143.2-168.8 GHz signal source with 5.6 dBm peak output power at 159 GHz and corresponding-94 dBc/Hz @ 1 MHz phase noise is reported. The circuit includes a 26 GHz Colpitts topology voltagecontrolled-oscillator and a static divide-by-four chains, an E-Band frequency tripler, a balanced D-Band frequency doubler. Through systematically analyzing the influence of input power level (detected by power detector) and base bias voltage on the output power of active frequency doubler, implementation of the D-Band doubler has been carefully designed to maximize output power of the signal source. Besides, by adopting high pass matching network in frequency tripler and frequency doubler design, the signal source exhibits an excellent unwanted harmonics suppression of over 30 dBc in the whole output tuning range. The total chip area is 2.4 mm 2 and the whole DC power consumption is 379 mW, which resulting in a peak DC-to-RF efficiency of 1.14 %. Compared with other D-Band signal sources, this signal source achieves the best phase noise (with divider chain), very competitive tuning bandwidth and the highest output power while using silicon-based processes with the lowest cutoff f T frequency.