A high-frequency track-and-hold stage with offset and gain compensation

Temes, Gábor C.; Huang, Yunteng; Ferguson, P.F.

doi:10.1109/82.404076

Cited by 15 publications

(8 citation statements)

References 1 publication

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“…Opamp gain and offset compensation utilizing predictive correlated double sampling (CDS) technique [6] [7] was adapted for this ADC. As illustrated in Fig.…”

Section: Simulation Resultsmentioning

confidence: 99%

Capacitor mismatch error cancellation technique for a successive approximation A/D converter

Zheng

Moon

Steensgaard

et al. 1999

1999 IEEE International Symposium on Circuits and Systems (ISCAS)

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An error cancellation technique is described for suppressing capacitor mismatch in a successive approximation A/D converter. At the cost of a 50% increase in the conversion time, the firstorder capacitor mismatch error is cancelled. Methods for achieving top-plate parasitic insensitive operation are described, and the use of a gain-and offset-compensated opamp is explained. SWIT-CAP simulation results show that the proposed 16-bit SAR ADC can achieve an SNDR of over 91 dB under non-ideal conditions, including 1% 3σ nominal capacitor mismatch, 10-20% randomized parasitic capacitors, 66 dB opamp gain, and 30 mV opamp offset.

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“…Opamp gain and offset compensation utilizing predictive correlated double sampling (CDS) technique [6] [7] was adapted for this ADC. As illustrated in Fig.…”

Section: Simulation Resultsmentioning

confidence: 99%

Capacitor mismatch error cancellation technique for a successive approximation A/D converter

Zheng

Moon

Steensgaard

et al. 1999

1999 IEEE International Symposium on Circuits and Systems (ISCAS)

Self Cite

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“…Also, since contains the input signal of the op-amp which generates , its cancellation boosts the effective op-amp gain and linearity [2]. The effective loop gain is approximately doubled in dB through this technique [2]. To reduce the input capacitance of this T/H, an extra capacitor can be used to store the voltage as is discussed in [3].…”

Section: Introductionmentioning

confidence: 97%

“…This cancels the input offset and reduces the 1/f noise of the op-amp during clock phase Φ 2 when C s is flipped around the op-amp. Also, since contains the input signal of the op-amp which generates , its cancellation boosts the effective op-amp gain and linearity [2]. The effective loop gain is approximately doubled in dB through this technique [2].…”

Section: Introductionmentioning

confidence: 98%

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Sequential interstage correlated double sampling: A switched-capacitor technique for high accuracy systems

Payandehnia

Maghami

Meng

et al. 2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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A novel sequential inter-stage correlated double sampling technique has been proposed. This technique provides considerable enhancement in the effective accuracy of a switched-capacitor architecture. Superior accuracy and thermal noise performance is achieved compared to the conventional correlated double sampling technique. The proposed approach provides higher input signal bandwidth by reducing the number of clock phases using a predictive phase compared to the other sequential techniques to achieve the same performance. Also, the proposed approach has the capability of driving both resistive and capacitive loads.

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“…In this paper, a novel stage (based on a modification of the circuit described in [6]) is proposed. It offers the following advantages:…”

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confidence: 99%

Switched-capacitor track-and-hold amplifier with low sensitivity to op-amp imperfections

Yoshizawa

Temes

2006

Analog Integr Circ Sig Process

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This paper describes a high-precision switchedcapacitor (SC) track-and-hold amplifier (THA) stage. It uses a novel continuous-time correlated double sampling (CDS) scheme to desensitize the operation to amplifier imperfections. Unlike earlier predictive-CDS THAs, the circuit does not need a sample-and-held input signal for its operation. During the tracking period, an auxiliary continuous-time signal path is established, which predicts the output voltage during the holding period. This allows accurate operation even for low amplifier gains and large offsets over a wide input frequency range. Extensive simulations were performed to compare the performance of the proposed THA with earlier circuits utilizing CDS. The results verify that its operation is far more robust than that of any previously described THA.

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A high-frequency track-and-hold stage with offset and gain compensation

Cited by 15 publications

References 1 publication

Capacitor mismatch error cancellation technique for a successive approximation A/D converter

Capacitor mismatch error cancellation technique for a successive approximation A/D converter

Sequential interstage correlated double sampling: A switched-capacitor technique for high accuracy systems

Switched-capacitor track-and-hold amplifier with low sensitivity to op-amp imperfections

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