In this paper the design of a voltage-mode switching mode amplifier in a 65-nm CMOS process in the GHz range is described. The amplifier can be operated with a rectangular drive signal with 50 % duty cycle up to 4 GHz and pseudo random bit sequences up to 4 GBit/s. The calibrated broadband PAE of the amplifier chip is 22 % at 2 GHz, 13 % at 3 GHz and 7 % at 4 GHz for a rectangular drive signal with 50 % duty cycle. The broadband output power into 50 Ω is 15.3 dBm for 2 GHz, 14 dBm for 3 GHz and 12 dBm for 4 GHz for a single ended measurement. Index Terms -CMOS integrated circuits, Broadband amplifiers, Microwave amplifiers I. INTRODUCTION In today's mobile communication systems high frequency power amplifier are usually linear power amplifiers. Despite their good linearity they suffer from bad efficiency. Switching mode amplifiers (SA) are very efficient. In theory a SA achieves 100 % efficiency. Recent publications show efficiencies beyond 75 % [1], [2]. A brief overview over recently published PAs is given in Table I. This paper describes a switching mode amplifier in a 65 nm CMOS process. Compared to SiGe or GaN the achievable PA bandwidth and the output power in CMOS are smaller. However CMOS itself is cheaper and the PA can be integrated onto the same die with the baseband processor. The breakdown voltage of the CMOS transistors is 1 V and thus small for power applications. In this paper a solution is presented how to achieve an output swing of 3 V by stacking the transistors.