A high IIP2 Gilbert mixer-based downconverter design for direct-conversion WiMAX receivers

Wu, Jiming; Ye, R. F.; Horng, Tzyy‐Sheng

doi:10.1109/rws.2010.5434233

Cited by 2 publications

(3 citation statements)

References 9 publications

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“…The comparison with other mixers recently reported in [2,8,10] shows that the performance of the proposed mixer is much better in terms of IIP2 ( Table 2). The other aspects are comparable but achieved with much larger RF operation bandwidth.…”

Section: Resultsmentioning

confidence: 78%

“…The second mechanism is device mismatches caused by process and the unbalanced stimulations. By referring to [10], the IIP2 can be expressed as…”

Section: Second-order Inter-modulation Distortionmentioning

confidence: 99%

“…The second-order inter-modulation products filtering technique [9] enhance the IIP2 by a filtering network, which is not suitable for a wide band down-converter. Adaptive biasing to the transistors of the switching stage [10] compensates the unbalance of the input LO signals to improve the IIP2 at the cost of conversion gain and power consumption. In order to get high linearity in a broadband without extra expense of conversion gain and power consumption, a fully differential semi-active down-conversion mixer with a prescaler to provide the balanced LO signals and a CMFB circuit to stabilize IM2 current is proposed.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 76-dBm IIP2 down-conversion mixer for TD-SCDMA/RFID applications

Jiang¹,

Zhang

Shi

et al. 2012

Analog Integr Circ Sig Process

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This paper presents a semi-active in-phase/ quadrature inductor-less down-conversion mixer. The mixer consists of an active trans-conductance stage, a passive current switching stage, and a trans-impedance stage. A complementary input architecture has been used to increase the trans-conductance for a given bias current. An on-chip prescaler is added to provide the balanced LO signals, while the CMFB circuit in trans-conductance stage is designed to enhance linearity. The chip was achieved in a 0.13 lm CMOS technology. It features 5 dB conversion gain over a broad range from 800 MHz to 2.1 GHz, which supports Chinese TD-SCDMA/RFID standards simultaneously. The maximum IIP2 is ?76 dBm at 2.1 GHz and suitable for application within a direct-conversion receiver.Keywords Semi-active mixer Á Quadrature Á CMOS radio frequency integrated circuit Á Direct-conversion receiver Á Input second-order intercept point Á TD-SCDMA Á RFID

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Section: Resultsmentioning

confidence: 78%

“…The second mechanism is device mismatches caused by process and the unbalanced stimulations. By referring to [10], the IIP2 can be expressed as…”

Section: Second-order Inter-modulation Distortionmentioning

confidence: 99%