A High IIP3, 50 GSamples/s Track and Hold Amplifier in 0.25 &amp;#181;m InP HBT Technology

Daneshgar, Saeid; Griffith, Z.; Rodwell, M.J.W.

doi:10.1109/csics.2012.6340112

Cited by 7 publications

(2 citation statements)

References 5 publications

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“…The base collector diode architecture offers a bandwidth even wider than that of the diode bridge T&H architecture. It also offers good linearity, a large dynamic range and good stability [5].…”

Section: Tandh Architecturesmentioning

confidence: 99%

A switched-capacitor based track-and-hold amplifier suitable for PAM4 signaling in 45-nm CMOS

Mokdad

Salameh

Atallah

2023

Analog Integr Circ Sig Process

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Test and measurement equipment often targets high bit-rate PAM4 signals that carry data at rates of several gigabits per second. These PAM4 signals are used to measure the quality of interconnects such as RF cables used in datacenters and deduce several important parameters such as the Bit Error Rate (BER) and the eye diagram, which in turn reveal information about the quality of the medium of transmission. In this paper, we propose the design of a track and hold (T&H) integrated circuit that is able to sample a high-speed incoming PAM4 signal and feed it to an Analog to Digital Converter (ADC). This building block acts as a front-end in optical transceivers carrying sensitive data, where power consumption and cost are a primary concern. The proposed architecture is discussed in detail and a design approach based on the switched capacitor architecture is examined and simulated. The circuit, implemented in a 45 nm CMOS technology, is able to sample an incoming 2 Gbit/s PAM4 signal at 0.2 GS/s, while consuming 42 mW of power and occupying 0.0225 mm 2 of area.

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Section: Tandh Architecturesmentioning

confidence: 99%

A switched-capacitor based track-and-hold amplifier suitable for PAM4 signaling in 45-nm CMOS

Mokdad

Salameh

Atallah

2023

Analog Integr Circ Sig Process

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“…These THA circuits need a large bandwidth, a good linearity, a high sampling rate with an excellent isolation and low losses during hold mode. High sampling and large bandwidth THAs are fabricated in InP [1, 2] or SiGe [3, 4] technologies. These THAs with 40 GSa/s [3] and 50 GSa/s [2, 4] sampling rate are based on a switched emitter follower (SEF) structure while the circuit presented in [1] uses base–collector diodes.…”

Section: Introductionmentioning

confidence: 99%

70 GSa/s and 51 GHz bandwidth track‐and‐hold amplifier in InP DHBT process

Deza

Ouslimani²,

Konczykowska

et al. 2013

Electron. lett.

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A differential 70 GSa/s track-and-hold amplifier has been designed and fabricated in a 320 GHz-f T InP double heterojunction bipolar transistor process. Measurements show a 51 GHz small-signal bandwidth with an S 11 parameter lower than −15 dB up to 56 GHz. The transient operation is verified up to 70 GSa/s. 60 GSa/s spectral measurements give total harmonic distortion <−46 dB up to 7 GHz and <−37 dB over the whole measurement range.Introduction: Most high sampling frequency and linear ADCs architectures often use one or several track-and-hold amplifiers (THAs) as input interface. ADC performances are based on those of the THA which is the main block. These THA circuits need a large bandwidth, a good linearity, a high sampling rate with an excellent isolation and low losses during hold mode. High sampling and large bandwidth THAs are fabricated in InP [1,2] or SiGe [3,4] technologies. These THAs with 40 GSa/s [3] and 50 GSa/s [2, 4] sampling rate are based on a switched emitter follower (SEF) structure while the circuit presented in [1] uses base-collector diodes. These circuits show small-signal bandwidths between 16 and 50 GHz.In this Letter we present a differential 70 GSa/s THA circuit fabricated in InP-DHBT with 50 GHz small-signal bandwidth. 70 GSa/s transient measurements are presented.

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An Active Track and Hold Circuit With Linearity Enhancement Technique and Its Analysis Using Volterra Series

Jang,

Lee,

Kim

2024

IEEE Access

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This paper presents a comprehensive analysis of active track and hold (T/H) circuits that utilize switched source followers and time-divided post-distortion cancellation. In the track phase, the circuit acts as an active buffer and transfers an input signal, including track-mode distortion caused by the buffer's nonlinear transconductance. In the hold phase, the transferred signal is held but hold-mode distortion is added, including hold-mode feed-through and hold pedestal error, causing deterioration of the circuit's linearity. The timedivided post-distortion cancellation technique improves the circuit's linearity by cancelling the track-mode distortion with the hold-mode distortion. Volterra series analysis offers a comprehensive understanding of the operation. 17 sample chips were measured to verify stable cancellation operation. It shows a mean SFDR value of 77.1 dB and a standard deviation of 1.8 dB with 9mW power consumption.

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A High IIP3, 50 GSamples/s Track and Hold Amplifier in 0.25 µm InP HBT Technology

Cited by 7 publications

References 5 publications

A switched-capacitor based track-and-hold amplifier suitable for PAM4 signaling in 45-nm CMOS

A switched-capacitor based track-and-hold amplifier suitable for PAM4 signaling in 45-nm CMOS

70 GSa/s and 51 GHz bandwidth track‐and‐hold amplifier in InP DHBT process

An Active Track and Hold Circuit With Linearity Enhancement Technique and Its Analysis Using Volterra Series

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