A high-level modeling framework for the design and optimization of complex CT functions

Abstract

Novel CMOS technologies are rapidly migrating towards the nanometer world. The design and optimization of complex analog circuits implying these processes is impracticable when using only transistor-level electronic design automation (EDA) tools. Efficient design methodologies including behavioral modeling are inevitable, but the high-level models should incorporate accurate circuit characteristics and technological limitations. One solution consists in using a refined top-down design process where the macro-models are extracted from the analog block elements (e.g. amplifiers, filters) implemented on specific technologies. These fast-simulating models can be used for the high-level simulation and optimization of the entire system. We propose in this paper a complete design methodology implying the above elements and the corresponding application framework based on the interface between MATLAB and CADENCE software tools. SIMULINK and VHDL-AMS are used for the high-level system modeling. A continuous-time (CT) Sigma-Delta modulator application is presented.

Efficient optimization methodology for CT functions based on a modified bayesian kriging approach

“…Once the system architecture is defined, the circuit design and the transistor level on a specific technology are implemented. Then, an automatic optimization process is performed on each cell using the MATLAB-CADENCE application framework [5]. The optimization process can be fully automatic, where the designer will select the input variables from the circuit and their existing range, the objectives and constraints, the number of starting points and the number of optimization points.…”

“…In terms of computation time, the optimization of an amplifier can take up to 5-10 hours, depending on the machine speed, the design complexity and the restrictions on the goals, but all is automatic and independent of the designer effort. Using the extracted macro-models, high-level implementations were conducted for different orders of models (2)(3)(4)(5)(6). MATLAB-SIMULINK and Dolphin Integration SMASH were used as simulators.…”