A high level synthesis design flow with a novel approach for efficient design space exploration in case of multi-parametric optimization objective

Sengupta, Anirban; Sedaghat, Reza; Zeng, Zhipeng

doi:10.1016/j.microrel.2009.11.015

Cited by 26 publications

(23 citation statements)

References 10 publications

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“…This section introduces a new mathematical PF model for clock oscillator resource, thus extending the authors" previous work [3]- [5] on PF model of functional resources. The Priority factor of the resources R1, …Rn (such as adders, multipliers etc) for the execution time is derived from [3]- [5].From [3]- [5], the priority factor for the resources R1,...Rn for execution time, is defined as:…”

Section: The Framework Used For Execution Timementioning

confidence: 88%

“…The model for the cost of the resources is proposed in this section and is an extension of the authors" previous work [3]- [5] on the area model.…”

Section: The Proposed Framework For Cost Modelmentioning

confidence: 99%

“…This paper proposes the use of a hierarchical tree topology for arrangement of design points in sorted orders and exploration of the optimal design point. Unlike the authors" previous works [3]- [5] using vector design space, this approach uses a more convenient topology for exploration. The tree structure is easy to construct and does not require a special algorithm to order the design space in increasing/decreasing order.…”

Section: System Specificationsmentioning

confidence: 99%

“…interpolation search and binary search. Previous works [3]- [5] employed a mono binary searching procedure. However, as highlighted in Fig.…”

Section: System Specificationsmentioning

confidence: 99%

“…The border variant obtained is variant "V5". After the border variants for both cost and execution time are found, the Pareto optimal set is derived as explained in [3]- [5]. The architecture tree for power consumption is constructed similarly in increasing orders of magnitude for power consumption.…”

Section: System Specificationsmentioning

confidence: 99%

See 4 more Smart Citations

Rapid exploration of cost-performance tradeoffs using dominance effect during design of hardware accelerators

Sedaghat

Sengupta

2014

FACTA U EE

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Modern Very Large Scale Integration (VLSI) designs require a tradeoff between cost efficiency and performance (circuit speed). Furthermore, the Design Space Exploration (DSE) of the cost-performance tradeoffs for the multi objective VLSI designs should also be fast and efficient in nature. This paper presents a novel accelerated DSE approach for the exploration of cost-performance tradeoffs of modular multi (trio parametric. viz. cost, execution time and power consumption) objective VLSI hardware accelerators using hierarchical criterion analysis. The selection of the final design point is made after the tradeoffs are explored using the proposed approach. Results of the proposed approach when applied to various benchmarks yielded significant acceleration in the exploration process compared to current existing approaches with multi parametric objective.

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