A high linearity 0.05–7 GHz digital step attenuator with the capacitive compensation for bonding wires parasitic parameters

Abstract

This paper presents a broadband, high linearity 7‐bit digital step attenuator (DSA) using a low‐cost bonding wire package. Capacitive compensation technique is proposed to offset the deterioration of attenuation accuracy and operating bandwidth caused by the parasitic parameters of the bonding wire and switching transistors. And the negative voltage bias technique (NVBT) is proposed to improve the linearity of the DSA. Based on the capacitive compensation technique and the NVBT, a 7‐bit DSA is implemented using a 0.13 µm Silicon‐On‐Insulator (SOI) process with a low‐cost bonding wire package. The DSA achieves broadband operation with an insertion loss (IL) of 2.7 dB at 7 GHz and root mean square (RMS) amplitude error less than 0.5 dB at DC‐7 GHz. The input P1 dB of all states is better than 31.7 dBm.