A High Linearity Driver with Embedded Interleaved Track-and-Hold Array for High-Speed ADC

In this brief, we propose a 60 GS/s high-linearity two-stage 8 × 8 time-interleaved track-and-hold circuit where it is possible to tune the static non-linearities of the second-stage buffer by applying a proper bias voltage. This allows us to maximize the static linearity of the buffer or introduce effects that counterbalance the non-linearities of other blocks of the analog front-end. To validate the proposed circuit, a prototype in TSMC 5 nm technology is designed and a linearity calibration loop is proposed for a Pulse Amplitude Modulation SerDes receiver. For the analog buffer, circuit-level simulations are performed in Cadence Virtuoso, while the calibration loop is simulated in MATLAB. The optimal bias voltage value can be found by modeling the track-and-hold linearity using a Taylor series and implementing the linearity calibration loop in MATLAB. By applying this result to the circuit-level simulation, we obtain a total harmonic distortion of over 50 dB, which matches with the maximum value achievable across the complete bias voltage control range. Lastly, the linearity of the system is also verified using a PAM-8 pseudorandom stream signal.

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“…The first stage is implemented through the sampling buffer described in [12]. In the second stage, eight interleaved buffers are used.…”

Section: Circuit Descriptionmentioning

confidence: 99%

A Track-and-Hold Circuit with Tunable Non-Linearity and a Calibration Loop for PAM-8 SerDes Receivers

Pasquo

Monaco²,

Ghittori³

et al. 2022

Electronics

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“…The circuit described in [13], which implements the first sampling stage (TH buf1), samples the signal on one of eight capacitances at a time. One input signal sample is taken every 16.7 ps.…”

Section: Circuit Implementationmentioning

confidence: 99%

A 60GS/s Two-Stage Sampler with a Linearity Calibration Loop for PAM-8 Receivers

Pasquo

Monaco²,

Ghittori³

et al. 2022

Electronics

Self Cite

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In this article, we show a 60 GS/s two-stage 8 × 8 time-interleaved sampling circuit, where the second-stage nonlinearity can be controlled by using the voltage that optimizes the static distortions of the sampler. A calibration algorithm can extract the nonlinear contributions of the stages and compensate for them by setting the optimal bias voltage. This can also be used to cancel the front-end nonlinear effects. The sampler was verified by implementing it in TSMC 5 nm FinFET, and a calibration system in a Pulse Amplitude Modulation transceiver, detecting and minimizing the nonlinearities, is presented. The optimum voltage biasing of the sampler was obtained by co-simulating the circuit with the linearity calibration loop implemented in Verilog-A. The histogram of the sampled signal at the slicer input is shown before and after the calibration to show the improvement in the sampled eye opening. Moreover, the resulting bias is equal to the one that maximizes the total harmonic distortion in transient simulations with a 1 GHz input signal, obtaining a minimum of 48.5 dB of total harmonic distortion across different PVT conditions.

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Analysis and Design of a High-Bandwidth Front-End Sampler for Time-Interleaved ADCs

Ding

Huang

et al. 2022

Circuits Syst Signal Process

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A High Linearity Driver with Embedded Interleaved Track-and-Hold Array for High-Speed ADC

Cited by 3 publications

References 7 publications

A Track-and-Hold Circuit with Tunable Non-Linearity and a Calibration Loop for PAM-8 SerDes Receivers

A Track-and-Hold Circuit with Tunable Non-Linearity and a Calibration Loop for PAM-8 SerDes Receivers

A 60GS/s Two-Stage Sampler with a Linearity Calibration Loop for PAM-8 Receivers

Analysis and Design of a High-Bandwidth Front-End Sampler for Time-Interleaved ADCs

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