A high linearity low power low-noise amplifier designed for ultra-wide-band receivers

Abstract

This paper presents a new ultra-wide band (UWB) CMOS low noise amplifier (LNA) with very high linearity and low power consumption for UWB wireless communication applications, where linearity is a big challenge, due to presence of interference and blocker signals, as well as the in-band harmonics of the desired signal components in the lower part of UWB band. The proposed LNA uses a new combination of saturated NMOS and PMOS transistors to improve both of second order and third order nonlinearities, meanwhile improving the noise performance and DC power consumption. In our design two techniques are integrated in a novel approach: Improved Complementary Derivative Superposition (ICDS) technique and Forward Body Bias (FBB) to reduce the threshold voltage of MOSFET, and hence, lowering the DC power. By utilizing a high-pass filter and common source stage in cascode form, wideband impedance matching and optimal noise figure (NF) have been obtained in the proposed UWB-LNA. The Post-layout simulation of the linearized LNA in a 180 nm RF CMOS process shows NF between 2.5 and 4 dB, gain of 10.8 ± 0.5 dB, and S 11 less than -10 dB in the entire 3.1-10.6 GHz band. Total DC power consumption is only 6 mW with 1.2 V supply voltage. The average and the maximum of IIP3 in the UWB band are ? 3.84 dBm and ? 7.27 dBm, respectively, a superior linearity performance compared to the reported UWB ones. The chip area is 926 mm 9 1075 mm, including the supply and ESD ring and the pads.

Innovative techniques for achieving flat response in a dual-resonance ultra-wideband low-noise amplifier

“…In this instance, the LNA is tailored for use in Wireless communication applications. The detailed metric goals of UWB-LNA for Wireless communication applications are provided in table 1 based on [15][16][17][18][19]. The LNA aims to achieve wide gain, low noise figure, excellent input-output reflection coefficient, stable operation, and efficient power.…”

Design and optimization of a CMOS IC novel RF tracking sensor

“…Previous works also reported designs to reduce intermodulation distortion through a frequency-selective capacitor (Jin et al 4 ), or a combination of saturated NMOS and PMOS transistors. 5 Intermodulation distortion is critical for this particular AoA sensing approach since any RF spurious/noise that is near the targeted frequency can add inaccuracy to sensing Δϕ. These unwanted spurious signals are difficult to filter out due to close-proximity frequency to f c , particularly third-order spurious signals like 2f 1 − f 2 or 2f 2 − f 1 .…”

“…The design goal of an LNA here targets to maintain low noise to restrain unwanted jitter and low DC offset and intermodulation distortion, which all contribute to inaccurate Δ φ measurements. Previous works also reported designs to reduce intermodulation distortion through a frequency‐selective capacitor (Jin et al 4 ), or a combination of saturated NMOS and PMOS transistors 5 . Intermodulation distortion is critical for this particular AoA sensing approach since any RF spurious/noise that is near the targeted frequency can add inaccuracy to sensing Δ φ .…”

Development of large terahertz heterodyne receiver arrays for future space observations

“…The room temperature LNA is not critical and can benefit from the development of the fifth generation (5G) of telecommunications networks, where the power consumption of the LNA is pushed down to an order of mW for each [109]. Due to the small size (~120 cm 3 ), low weight (~120 g), and low power consumption (1.5 W) of the CMOS chip-based spectrometer [110], it is feasible to design the kilo-pixel array.…”