A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1

Wang, Zhenyu; Wang, Mingshuo; Gu, Weizhong; Chen, Chixiao; Ye, Fan; Ren, Junyan

doi:10.1109/tcsi.2013.2252643

Cited by 24 publications

(5 citation statements)

References 25 publications

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“…4 presents the details of the improved bootstrapped switch. A floating-well technique described in [4], [15] is applied to optimize the nonlinear capacitance of the diode J1. Specifically, during the hold phase, the isolation layer is reset to VDD via M10.…”

Section: A Parasitics In Conventional Bootstrapped Switchmentioning

confidence: 99%

“…High-frequency and high-resolution pipelined ADCs have imposed stringent requirements on clock designs, including low jitter property for SHA, precise duty cycle for pipeline stages, and non-overlapping clocks for voltage sampling and charge transferring [4], [20], [21]. First, clock jitter leads to sample-to-sample variations, which can result in prominent errors for IF-sampling applications because of the high slew rate of fast changing input signals.…”

Section: Clock Design Schemementioning

confidence: 99%

“…Benefiting from the IF/RF sampling ability, the architecture of cellular base stations evolves from multi-narrowband receivers to a single wideband multi-channel receiver, which transfers the major work of individual channel extraction to mature digital signal processing and hence significantly reduces the cost and complexity of cellular base stations [1]- [4]. Other applications such as cable modems, CCD medical imaging, and computed tomography scanners have similar quantization requirements [3], [5], [6].…”

Section: Introductionmentioning

confidence: 99%

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A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

Zheng

Wang

et al. 2016

IEEE Trans. Circuits Syst. I

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Abstract-This paper presents a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. Moreover, a partial non-overlapping clock scheme associated with a highspeed reference buffer and fast comparators is proposed to maximize the residue settling time. The implemented ADC is measured under different input frequencies with a sampling rate of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30 MHz input, the measured SFDR and SNDR of the ADC is 94.7 dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for up to 400 MHz. The measured DNL and INL after calibration are optimized to 0.15 LSB and 1.00 LSB, respectively, while the Walden FOM at Nyquist frequency is 0.57 pJ/step.

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Section: A Parasitics In Conventional Bootstrapped Switchmentioning

confidence: 99%

Section: Clock Design Schemementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

Zheng

Wang

et al. 2016

IEEE Trans. Circuits Syst. I

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“…The ADC core consists of an SHA as the sampling front-end and 7 back-end MDACs, among which MDAC1-MDAC6 are 2.5-bit with an extra 0.5-bit as redundancy, and the MDAC7 is 2-bit. In order to meet up with the low-power requirement, SHA and MDAC1 share the second stage of the op-amp by using the split op-amp sharing techniques mentioned in Reference [2]. MDAC2 and MDAC3 share the op-amp AMP2, while MDAC4 and MDAC5 share the op-amp AMP.…”

Section: Adc Architecturementioning

confidence: 99%

“…In this proposed ADC, the SHA and MDAC1 are implemented by applying the split op-amp sharing techniques in Reference [2]. While in the following stages, the normalized power of the op-amps can be listed as: (n D 2.5, D 0.7, Á D 0.9).…”

Section: Op-amp Sharing Strategymentioning

confidence: 99%

14-bit 100 MS/s 121 mW pipelined ADC

Chen

Feng

et al. 2015

J. Semicond.

Self Cite

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This paper presents a high-speed high-resolution pipelined ADC with low power and small area. The proposed ADC is designed based on the analysis of the stage scaling theory and the residual amplifiers are shared by two cascading MDACs to reduce power consumption. Shared op-amps with two split input paths are presented in this paper to eliminate the nonlinearity effects such as memory effect and crosstalk. Dynamic pre-amplified comparators are employed to decrease the static power consumption and suppress the kick-back in the comparators. This ADC is implemented in SMIC 0.18 μm CMOS process with an area of 3.1 mm2. With a sampling rate of 100 MS/s, spurious-free dynamic range (SFDR) and signal-to-noise plus distortion ratio (SNDR) of the ADC are 82.7 dB and 69.1 dB, respectively. For signals up to 100 MHz, the SFDR and SNDR achieve 81.4 dB and 65.8 dB. The power consumption is 121 mW with a 1.8 V supply voltage.

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A 1.0 V, 9.84 fJ/c-s FOM reconfigurable hybrid SAR-sigma delta ADC for signal processing applications

Adimulam

Srinivas

2019

Analog Integr Circ Sig Process

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A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1

Cited by 24 publications

References 25 publications

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

14-bit 100 MS/s 121 mW pipelined ADC

A 1.0 V, 9.84 fJ/c-s FOM reconfigurable hybrid SAR-sigma delta ADC for signal processing applications

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