A high output swing current-steering DAC using voltage controlled current source

Huang, Qinjin; Yu, Fengqi

doi:10.1016/j.mejo.2017.08.014

Cited by 8 publications

(10 citation statements)

References 12 publications

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“…So relatively poor frequency performances at high frequency is acceptable. Comparing with [7] and [5], this work achieves higher resolution number at similar cost. Comparing with [8], this work achieves higher working speed.…”

Section: Measurement and Comparisonmentioning

confidence: 88%

“…In order to estimate the overall performance, the figure-ofmerit (FOM) and area efficiency (AE) are introduced [5,13,14]. The FOM measures the achievable resolution and speed per unit die size and power.…”

Section: Measurement and Comparisonmentioning

confidence: 99%

“…The measurement results of R-I DAC in [4] are 9-bit precision, 1.74 mW power consumption, and 20 MSps speed [4]. Although R-I DAC has many merits, its lowest output voltage can only reach 0.4 V. As 0.4 V accounts for a third of 1.2 V supply voltage, the available signal swing is too small, making R-I DAC not practical [4,5,6]. So it is necessary to increase the output swing of R-I DAC for low-voltage and low-power applications.…”

Section: Introductionmentioning

confidence: 99%

“…But it has a low-speed (200 KSps), which is not acceptable in many medical implantable applications either. In 2017, Huang and Yu used a voltage-controlled-current-source to generate a biasing current in order to eliminate the limitation of output swing [5]. The biasing current flows through the feedback resistor, generating a voltage drop at the output.…”

Section: Introductionmentioning

confidence: 99%

“…To further decrease the power consumption of [5], in this paper, we propose a novel R-I DAC with current-direction control. We adopt a PMOS current mirror to eliminate the output swing limitation of the R-I DAC.…”

Section: Introductionmentioning

confidence: 99%

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A 10-bit 0.41-mW 3-MSps R-I DAC with full-swing output voltage

Huang

2018

IEICE Electron. Express

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For medical implantable devices, power consumption is the most important design consideration. This is because only medium data rate and medium resolution are required in such applications. In addition, rail-to-rail output swing is desired if power supply voltage is near 1 V. In order to achieve low power consumption with medium data rate and resolution, this paper proposes a low-power resistor-string and current-steering hybrid digital-to-analog converter (R-I DAC) with a full-swing output signal. It adopts a current-direction control which makes the output current of the current-steering block flow bi-directionally through the feedback resistor. The proposed structure can achieve full-swing output. It consumes half of the total current of the conventional single-ended current-steering DAC for the same output swing. A 10-bit full-swing R-I DAC prototype is implemented by 180-nm CMOS technology. The measured effective number of bits (ENOB) is 8.9 bits. The settling time of pulse response is 300 ns which corresponds to 3.3 MHz sampling frequency. Chip area is 0.22 mm 2 . For 1.25 V single power supply, the output swing is 1.024 V. The power consumption is 0.41 mW for a full-swing sinusoidal input of 40.82 kHz at a 3.125 MS/s sampling clock.

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Section: Measurement and Comparisonmentioning

confidence: 88%

Section: Measurement and Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A 10-bit 0.41-mW 3-MSps R-I DAC with full-swing output voltage

Huang

2018

IEICE Electron. Express

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Design of a high speed 14‐bit digital to analog converter circuit

Tang

Chen

2020

Trans Emerging Tel Tech

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A 14-bit current domain digital to analog converter (DAC) is presented, which employs 4 + 4 + 6 segmented current-steering architecture. The high 4-bit and intermediate 4-bit adopted thermometer code control, and the low-6 bit used direct control of binary weighted current source, so the dynamic performance of DAC is improved. The detailed design of the core modules of DAC is also given, including high-precision programmable reference current source, DAC encoding and decoding circuit, and the current source array. The DAC is fabricated in SMIC 0.18 μm 1P6M CMOS technology. The simulation results of Hspice show that the spurious free dynamic range for 80 MHz output signal at 400 MHz sampling clock rate is 72.47 dB, and the design has met the requirements.

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