2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) 2003
DOI: 10.1109/vlsit.2003.1221098
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A high performance 90 nm logic technology with a 37 nm gate length, dual plasma nitrided gate dielectric and differential offset spacer

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“…3(b) & (c)) and the "native" TSMC structure in the Altera chip. The outer sidewall spacers are Lshaped, and TI's extra differential offset spacers [5] were present for tuning of the source-drain extensions. We can also see that the NMOS nitride spacers have implant damage, indicating the use of memorized stress.…”
Section: Tsmc/texas Instruments/nokia 4377401 Baseband Socmentioning
confidence: 99%
“…3(b) & (c)) and the "native" TSMC structure in the Altera chip. The outer sidewall spacers are Lshaped, and TI's extra differential offset spacers [5] were present for tuning of the source-drain extensions. We can also see that the NMOS nitride spacers have implant damage, indicating the use of memorized stress.…”
Section: Tsmc/texas Instruments/nokia 4377401 Baseband Socmentioning
confidence: 99%