A High-Performance and Energy-Efficient TCAM Design for IP-Address Lookup

Chang, Yen-Jen

doi:10.1109/tcsii.2009.2020935

Cited by 25 publications

(4 citation statements)

References 11 publications

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“…It also facilitates the parallel search operation, which accelerates these searches. TCAMs have been proposed to realize an Associative Memory (AM) [18] and are currently used in CPU caches or network routers [19], [20]. A single TCAM cell is typically implemented using two SRAM cells and access logic at a total of 16 CMOS transistors.…”

Section: B Fefet-based Ternary Content Addressable Memorymentioning

confidence: 99%

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

Kumar

Chatterjee

Thomann

et al. 2023

IEEE Trans. Circuits Syst. I

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Today's data-centric applications are incompatible with the predominant compute-centric computer architectures. The small on-chip memories of compute-centric computer architecture demand many energy-costly data transfers exposing the von-Neumann bottleneck. The Ferroelectric Field-Effect Transistor (FeFET) is an emerging Non-Volatile Memory (NVM) technology enabling novel data-centric architectures that go far beyond von-Nuemann principles. FeFETs are very promising for a wide range of applications starting from on-chip memories to in-memory computing and even neuromorphic computing. Nevertheless, FeFET devices exhibit significant variations that can severely restrict their applicability. Temperature further exacerbates variation effects because it degrades ferroelectric parameters. Hence, it is indispensable to investigate and model design-time variations, run-time variations, and stochastic variations due to spatial fluctuation of ferroelectric domains under different temperatures. Dual-port FeFET has been recently proposed and demonstrated as novel structure that offers for the first time disturb-free read operation along with > 10 larger memory window (MW) compared to conventional FeFETs. However, all of the before-mentioned types of variations are amplified in such a new structure. In this work, the impact of temperature variation is analyzed for dual-port FeFETs for the first time in a cross-layer manner starting from the device level to the circuit/system levels and compared to conventional FeFET.We focus in our analysis on Hyperdimensional Computing (HDC), which is an emerging type of machine learning algorithm, that is being executed on top of FeFET-based in-memory circuits that perform efficient Hamming distance (i.e., similarity) computations. Through our cross-layer framework, we demonstrate the serious impact of variation on FeFET reliability despite the significant increase in the MW that dual-port FeFET offers. Even HDC is affected, despite its remarkable robustness against errors. All in all, our work reveals that a larger MW at the device level does not necessarily translate to benefits at the application level. Hence, investigating and modeling variability effects in a crosslayer manner is indispensable.

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Section: B Fefet-based Ternary Content Addressable Memorymentioning

confidence: 99%

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

Kumar

Chatterjee

Thomann

et al. 2023

IEEE Trans. Circuits Syst. I

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“…Hamming distance is the most straightforward metric for approximate search in BCAMs/TCAMs. CAMs, which are traditionally used in routers and caches (Karam et al, 2015;Yin et al, 2020), have been gaining popularity in data-intensive applications such as nearest neighbor search (Kohonen, 2012;Kazemi et al, 2020Kazemi et al, , 2021b, bioinformatics (Laguna et al, 2020), neural networks (Chang, 2009;Wang et al, 2010;Li C. et al, 2020, Li et al, 2021Kazemi et al, 2021a), etc. CAMs also have been used in implementing LSH-based attention (Ni et al, 2019).…”

Section: Circuitsmentioning

confidence: 99%

Hardware-Software Co-Design of an In-Memory Transformer Network Accelerator

Laguna¹,

Sharifi²,

Kazemi³

et al. 2022

Front.Electron.

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Transformer networks have outperformed recurrent and convolutional neural networks in terms of accuracy in various sequential tasks. However, memory and compute bottlenecks prevent transformer networks from scaling to long sequences due to their high execution time and energy consumption. Different neural attention mechanisms have been proposed to lower computational load but still suffer from the memory bandwidth bottleneck. In-memory processing can help alleviate memory bottlenecks by reducing the transfer overhead between the memory and compute units, thus allowing transformer networks to scale to longer sequences. We propose an in-memory transformer network accelerator (iMTransformer) that uses a combination of crossbars and content-addressable memories to accelerate transformer networks. We accelerate transformer networks by (1) computing in-memory, thus minimizing the memory transfer overhead, (2) caching reusable parameters to reduce the number of operations, and (3) exploiting the available parallelism in the attention mechanism computation. To reduce energy consumption, the following techniques are introduced: (1) a configurable attention selector is used to choose different sparse attention patterns, (2) a content-addressable memory aided locality sensitive hashing helps to filter the number of sequence elements by their importance, and (3) FeFET-based crossbars are used to store projection weights while CMOS-based crossbars are used as an attentional cache to store attention scores for later reuse. Using a CMOS-FeFET hybrid iMTransformer introduced a significant energy improvement compared to the CMOS-only iMTransformer. The CMOS-FeFET hybrid iMTransformer achieved an 8.96× delay improvement and 12.57× energy improvement for the Vanilla transformers compared to the GPU baseline at a sequence length of 512. Implementing BERT using CMOS-FeFET hybrid iMTransformer achieves 13.71× delay improvement and 8.95× delay improvement compared to the GPU baseline at sequence length of 512. The hybrid iMTransformer also achieves a throughput of 2.23 K samples/sec and 124.8 samples/s/W using the MLPerf benchmark using BERT-large and SQuAD 1.1 dataset, an 11× speedup and 7.92× energy improvement compared to the GPU baseline.

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“…The benefits of IMC mainly arise from the high parallelism that can be achieved through a dense array of memory units executing computations simultaneously. IMC can be realized through the use of classical CMOS technologies [17][18][19][20][21][22] or beyond-CMOS technologies [23][24][25][26][27][28][29][30][31][32][33][34][35][36][37] . Authors in 20 have demonstrated the use of IMC for Quantum Error Correction using the conventional 6-T SRAM cell based on 28 nm CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

Cryogenic Brain-inspired Hyperdimensional In-Memory Computing using 5nm Ferroelectric FinFET

Parihar,

Kumar,

Chatterjee

et al. 2024

Preprint

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The pursuit of large-scale quantum computing has captivated the scientific community, and the potential of cryogenic circuits using mature CMOS technologies represents a significant step forward in this quest. Nevertheless, the operation of circuits at cryogenic temperatures poses significant challenges due to the strict power and timing constraints. These challenges are compounded by the well-known Von Neumann bottleneck that plays a major role in limiting the throughput and energy efficiency of modern computing systems. To overcome such a bottleneck, In-Memory Computing (IMC) is rapidly emerging as a promising solution for creating hardware accelerators that go far beyond Von Neumann principles, offering substantial efficiency improvements. In this work, we investigate the effectiveness of cryogenic brain-inspired hyperdimensional IMC using emerging Ferroelectric (FE) technologies at the 5 nm node. To achieve that, we begin by characterizing commercial 5 nm FinFETs from room temperature (300 K) down to cryogenic temperature (10 K). Then, we carefully calibrate the first industry-standard cryogenic-aware compact model (BSIM-CMG) to accurately reproduce the measurements. Afterward, we incorporate a physics-based FE model within the BSIM-CMG model and calibrated it against FE capacitor measurements to realize Fe-FinFET devices operating from 300 K down to 10 K. Then, as proof of concept, we focus on 1×8 Ternary Content Addressable Memory (TCAM) array that we use to perform the language classification using brain-inspired hyperdimensional IMC. Our comprehensive analysis spans from investigating the delay, power, and energy efficiency of IMC-based TCAM all the way up to calculating error probabilities in which we compare the figure of merits obtained from the emerging Fe-FinFET against classical FinFET-based IMC.

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A High-Performance and Energy-Efficient TCAM Design for IP-Address Lookup

Cited by 25 publications

References 11 publications

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

Hardware-Software Co-Design of an In-Memory Transformer Network Accelerator

Cryogenic Brain-inspired Hyperdimensional In-Memory Computing using 5nm Ferroelectric FinFET

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