2009 Sixth International Conference on Information Technology: New Generations 2009
DOI: 10.1109/itng.2009.50
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A High-Performance Architecture of an XML Processor for SIP-Based Presence

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Cited by 5 publications
(3 citation statements)
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“…In the architecture (Fig. 5), the SIP engine [10] performs the functionality for SIP, while the XML engine [11] processes the SIP presence of PIDF format. Both engines share a common interface so data can be successfully transferred to and from software.…”
Section: A High Level Architecturementioning
confidence: 99%
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“…In the architecture (Fig. 5), the SIP engine [10] performs the functionality for SIP, while the XML engine [11] processes the SIP presence of PIDF format. Both engines share a common interface so data can be successfully transferred to and from software.…”
Section: A High Level Architecturementioning
confidence: 99%
“…A hardware implementation of SIP is discussed in [10] illustrating an architecture to implement SIP with selected SIP extensions with optimal performance. An architecture for processing XML for SIP presence is introduced in [11] describing how XML based payloads describing user presence can be parsed and generated in hardware with SIP packets. This paper discusses how these hardware implementations can be used to provide IMS functionality in hardware.…”
Section: Introductionmentioning
confidence: 99%
“…Some research has occurred in the literature on this topic like the work discussed in [11], [12], [13] and [14]. The Reconfigurable Multimedia Collaborative System (RMCS) [15] is a robust FPGA-based implementation of SIP and selected extensions that provide the foundation for the work described in [16], [17] and [18].…”
Section: Introductionmentioning
confidence: 99%