A high‐performance CMOS four‐stage amplifier

Abstract

In this paper, we theoretically propose and mathematically describe an effective four‐stage structure in Complementary metal‐oxide‐semiconductor (CMOS) technology based on differential block feedback. The special architecture of frequency compensation network improves frequency response with very small value of compensation capacitor, which results in low die area occupation. The presented novel and simple four‐stage structure is frequency compensated just via single Miller capacitor and a differential block. Symbolical transfer function is calculated, and circuit dynamics are introduced. To well explain theoretical description, the proposed configuration at circuit level is simulated using Taiwan Semiconductor Manufacturing Company Limited (TSMC) 0.18‐μm CMOS technology and HSPICE circuit simulator. The proposed configuration and corresponding circuit benefits from circuit simplicity and low die‐area occupation. The frequency compensation network forms two Miller loops with negative loop gains. Feedback paths are amplified via differential block while feedforward paths are attenuated, leads to improving frequency response compare with conventional structures. Ample simulation results are in good agreement with theoretical description. Leveraging the concept and method proposed four‐stage amplifier exhibits 170 dB, 8.12 MHz, and 90° as direct current (DC) gain, Gain‐BandWidth Product (GBW), and Pase Margin (PM), respectively. The supply voltage is set to 1.8 V, while the simulated circuit consumes 380 μW.

Four‐stage CMOS operational transconductance amplifier: Compensated via double differential blocks

“…So, exploiting frequency compensation methods becomes an inevitable task to achieve stable amplification, at least conditionally. [8][9][10][11] In this regard, numerous frequency compensation approaches are reported by scientists, mainly for three-stage amplifiers. It should be noted that two-stage structures can be frequency compensated via a single Miller capacitor and available DC-gain is limited to less than 100 dB.…”

“…But the problem turns to stability issues due to the increasing number of nods, knowing that each node poses a pair of pole‐zero to the system. So, exploiting frequency compensation methods becomes an inevitable task to achieve stable amplification, at least conditionally 8–11 . In this regard, numerous frequency compensation approaches are reported by scientists, mainly for three‐stage amplifiers.…”

Five‐stage CMOS OTAfrequency compensated via nested differential feedback

“…Logically, more nodes in amplifier leads to more complicated compensation network. [18][19][20][21][22][23][24][25][26] So, design simplicity attracts attention since complex structures are less reliable for many reasons such as fabrication mismatches and heavy theoretical calculations. In this regard, in this paper a five stage transconductance amplifier with related compensation network is proposed, described and simulated.…”

Four‐stage CMOS amplifier design based on symbolic calculations: Stack comparison approach

“…However, the above operators do not consider these correlations. (2) The simple replacement of circuit parameters with corresponding ranges and the use of high operators give rise to very wide sentences variation and polynomials, which have been taken too carefully 10‐13 . For example, for one parameter in some sentences the maximum range is set, whereas for the same parameter in other sentences the minimum value is set.…”