A high performance deblocking filter hardware for High Efficiency Video Coding

FPGA implementation of a HEVC deblocking filter for fast processing of super high resolution applications

“…It can be observed from Table 2 that the proposed architecture has a lower gate count than that from [9] and [10] but not [5] and [11]; however, clock cycles required by [5] and [11] are much greater than the proposed one. [10] achieved fewer clock cycles at the cost of using large size memories and higher gate count.…”

“…[10] achieved fewer clock cycles at the cost of using large size memories and higher gate count. The resolution used in [5] is 1080p and is four times less than that of all the other architectures. We have achieved a faster architecture in our design than [5] but at the stake of larger gate count.…”

“…The resolution used in [5] is 1080p and is four times less than that of all the other architectures. We have achieved a faster architecture in our design than [5] but at the stake of larger gate count. The main reason for the better results of the proposed architecture is the use of small size distributed memories and parallel filtering.…”

“…The filtering in HEVC is less complex and more efficient than the deblocking filter of the previous H.264 standard [5]. The DBF in HEVC employs parallel filtering to improve subjective and objective quality by suppressing and removing blocking artifacts [6].…”

A computation and energy reduction technique for HEVC intra mode decision

“…- [4]. HEVC has 36% better compression efficiency than H.264 which is the current state-of-the-art video compression standard.…”