A high performance deblocking filter hardware for high efficiency video coding

Özcan, Erdem; Adibelli, Yusuf; Hamzaoğlu, İlker

doi:10.1109/tce.2013.6626260

Cited by 43 publications

(20 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The comparison among some previous work and the proposed design is drawn in Table II. As Table II shows, our design can achieve 318MHz TABLE II. PLEMENTATIONS COMPARIS working frequency at most, which makes it capable of supporting 8kx4k@90fps and it is much higher than [5] and [7]. The throughput in [6] is close to ours, however it does not consider the cycles of data loading and output.…”

Section: Implementation Resultsmentioning

confidence: 90%

“…In [5], two parallel data paths with 10 SRAMs were applied to increase its performance with the cost of larger areas and memory management complexity, meanwhile its performance is not very high which can only support 1920x1080@30fps real time encoding. In [6], an architecture with a novel memory interlacing organization and four-stage pipeline is proposed, however it only processes 32x32 LCU and the pixels loading and output are not considered.…”

Section: Introductionmentioning

confidence: 99%

“…In [7], an architecture combining Deblocking and SAO which can reach 266 MHz at most in 28 nm CMOS technology is proposed, however the throughout is 8kx4k@20fps which can't support 8kx4k real time encoding. In fact, the filter procedure optimization is not considered or mentioned in [5], [6] and [7].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application

Cheng

Fan

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

As the next generation of video coding standard, High Efficiency Video Coding (HEVC) aims to reduce 50% bit rates in comparison with previous video coding standards. In order to increase the Deblocking Filter (DBF) throughput, we propose a memory of ping-pong and interlacing VLSI architecture to prevent DBF from unnecessarily waiting for pixels in both vertical and horizontal, which only takes 435 cycles at worst to process a LCU of 64x64 pixels size. Based on the memory organization, a four stage pipeline with a PreFilter was proposed to eliminate the data dependence in the filter processing and makes it working on 318M possible. As a result, our design can support 8kx4k@90fps real-time applications with SMIC 0.13um technology at the cost of 62.9k gates.

show abstract

Section: Implementation Resultsmentioning

confidence: 90%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application

Cheng

Fan

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

“…[4] and [5], while achieves much higher system throughput. Compared with the HEVC DBF design in [6], the proposed architecture achieves much higher throughput than the 2-path implementation with a little cost increase, and it reaches both higher throughput and lower cost than the 6-path one. The design in [7] achieves a quite high system throughput by employing four parallel filters, which also results in a large hardware cost.…”

Section: B Filtering Order and Memory Organizationmentioning

confidence: 99%

“…A hardware DBF design for HEVC with parallel data-paths was proposed in [6] and a four-stage pipeline architecture was presented in [7]. To support real-time processing of high definition videos, parallel architectures were adopted in both of them.…”

Section: Introductionmentioning

confidence: 99%

A cost-efficient hardware architecture of deblocking filter in HEVC

Ding

2014

2014 IEEE Visual Communications and Image Processing Conference

View full text Add to dashboard Cite

This paper presents a hardware architecture of deblocking filter (DBF) for High Efficiency Video Coding (HEVC) by jointly considering system throughput and hardware cost. A hybrid pipeline with two processing levels is adopted to improve system performance. With the hybrid pipeline, only one 1-D filter and single-port on-chip SRAM are used. According to the data dependence between neighbouring edges, a shifted 16×16 basic processing unit as well as corresponding filtering order is proposed. It reduces memory cost and makes the DBF friendlier to work in a coding/decoding system. The proposed hardware architecture is synthesized under 0.13um standard CMOS technology and result shows that it consumes 17.6k gates at an operating frequency of 250MHz. Consequently, the design can support real-time processing of QFHD (3840×2160) video applications at 60 fps.

show abstract

An Efficient Hardware Architecture for Deblocking Filter in HEVC

Kopperundevi

Prakash

2020

Lecture Notes in Electrical Engineering

View full text Add to dashboard Cite

A high performance deblocking filter hardware for high efficiency video coding

Cited by 43 publications

References 13 publications

A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application

A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application

A cost-efficient hardware architecture of deblocking filter in HEVC

An Efficient Hardware Architecture for Deblocking Filter in HEVC

Contact Info

Product

Resources

About

A high performance deblocking filter hardware for high efficiency video coding

Cited by 43 publications

References 13 publications

A high-throughput HEVC deblocking filter VLSI architecture for 8k&#x00D7;4k application

A high-throughput HEVC deblocking filter VLSI architecture for 8k&#x00D7;4k application

A cost-efficient hardware architecture of deblocking filter in HEVC

An Efficient Hardware Architecture for Deblocking Filter in HEVC

Contact Info

Product

Resources

About

A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application

A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application