A High-Performance ECC Processor Over Curve448 Based on a Novel Variant of the Karatsuba Formula for Asymmetric Digit Multiplier

Abstract

In this paper, we present a high-performance architecture for elliptic curve cryptography (ECC) over Curve448, which to the best of our knowledge, is the fastest implementation of ECC point multiplication over Curve448 to date. Firstly, we introduce a novel variant of the Karatsuba formula for asymmetric digit multiplier, suitable for typical DSP primitive with asymmetric input. It reduces the number of required DSPs compared to previous work and preserves the performance via full parallelization and pipelining. We then construct a 244-bit pipelined multiplier and interleaved fast reduction algorithm, yielding a total of 12 stages of pipelined modular multiplication with four stages of input delay. Additionally, we present an efficient Montgomery ladder scheduling with no additional register is required. The implementation on the Xilinx 7-series FPGA: Virtex-7, Kintex-7, Artix-7, and Zynq 7020 yields execution times of 0.12, 0.13, 0.24, and 0.24 ms, respectively. It increases the throughput by 242% compared to the best previous work on Zynq 7020 and by 858% compared to the best previous work on Virtex-7. Furthermore, the proposed architecture optimizes nearly 63% efficiency improvement in terms of Area×Time tradeoff. Lastly, we extend our architecture with well-known side-channel protections such as scalar blinding, basepoint randomization, and continuous randomization.INDEX TERMS elliptic-curves cryptography (ECC); Curve448; high-speed multiplier; asymmetric Karatsuba; field-programmable gate array (FPGA)

DCryp-Unit: Crypto Hardware Accelerator Unit Design for Elliptic Curve Point Multiplication

“…Instead of hardware accelerators of [6], [11]- [13], [15] over binary field lengths, prime field over GF (P ) with P = 256 is considered in [14], [17], [19] for hardware acceleration. One accelerator over special ECC Curve448 is described in [21]. On identical Virtex-7 FPGA, the utilized LUTs in [14] are 1.90 (a ratio of 23k to 12113) times higher than our hardware accelerator.…”

“…An area-time efficient point multiplication architecture on a twisted Edwards curve is described in [20]. A highperformance ECC processor architecture over curve448 is presented in [21], where a novel variant of the Karatsuba formula for asymmetric digit multiplier is incorporated for polynomial multiplications. The work described in [22] offers high-speed and reconfigurable polynomial multiplication architectures for specific prime fields.…”

“…The limitations in the related hardware accelerators are that most of the accelerators such as [6], [11]- [13], [17]- [21], [23], [29]- [32] lack a discussion regarding the power consumption of their circuits. This aspect is particularly critical for a wide range of constrained applications, including radio-frequency identification networks (RFID), wireless sensor networks (WSNs), and Internet of Things (IoT) [33]- [37].…”

“…Instead of the area, we surpass operating frequency, latency, throughput, and FoM values, as evident in Table 2. As shown in Table 2, on Virtex-6 and Virtex-7 devices, our accelerator utilizes lower hardware resources and is more efficient in computation time, throughput, and FoM values as compared to other prime field accelerators of [17], [19], [21]. This is due to the different ECC fields and the supported key lengths.…”

Depth-Optimization of Quantum Cryptanalysis on Binary Elliptic Curves

“…Like the extensive use of ECCs as mentioned in the [9] survey research on ECC hardware implementation, constructing various arithmetic operations efficiently in ECC circuits has become increasingly crucial as hardware and quantum computing research have evolved. In this research, the ECC implementations are categorized into two main groups based on their implementation technologies: field programmable gate array (FPGA)-based implementations [10] and application-specific integrated circuit (ASIC)-based implementations [11].…”