A high-performance, high-density 28nm eDRAM technology with high-K/metal-gate

Huang, Kevin; Yang, Tao; Chang, Chin-Ho; Tu, K.C.; Tzeng, K. C.; Chu, H.C.; Pai, C.Y.; Katoch, A.; Kuo, Way; Chen, K.W.; Hsieh, T.H.; Tsai, Cary Chi‐Liang; Chiang, Wen−Jen; Lee, H.F.; Achyuthan, A.; Chen, C.Y.; Chin, H.W.; Wang, M.J; Wang, C.J.; Tsai, C.S.; O'Connell, C.; Natarajan, S.; Wuu, Shou-Gwo; Wang, Isabel; Hwang, H. Y.; Tran, L.C.

doi:10.1109/iedm.2011.6131608

Cited by 17 publications

(9 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The density rapidly worsens if S increases. Without scaling, the Z 2 -FET bit cell is almost 2.4 times larger than typical eDRAM for the same technological node [15], table IV. By symmetrically scaling the devices without any structure enhancement, the bit cell area ratio decreases to 1.5.…”

Section: Edram Density Integration Comparisonmentioning

confidence: 96%

See 1 more Smart Citation

${Z}^{\textsf {2}}$ -FET as Capacitor-Less eDRAM Cell For High-Density Integration

Navarro

Duan

Parihar

et al. 2017

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

Abstract-2D numerical simulations are used to demonstrate the Z 2 -FET as a competitive embedded capacitor-less DRAM cell for low-power applications. Experimental results in 28 nm FD-SOI technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature.

show abstract

Section: Edram Density Integration Comparisonmentioning

confidence: 96%

“…If one selector is shared for each wordline, A bit is given by: [15]. L S = 28 nm and A Over = 50 %.…”

Section: Edram Density Integration Comparisonmentioning

confidence: 99%

${Z}^{\textsf {2}}$ -FET as Capacitor-Less eDRAM Cell For High-Density Integration

Navarro

Duan

Parihar

et al. 2017

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

show abstract

“…For instance, a read access to a 256-bit wide eDRAM array at 28nm consumes 0.0192nJ (50μA, 0.9V, 606 MHz) [25], while a 256-bit read access to a Micron DDR3 DRAM consumes 6.18nJ at 28nm [40], i.e., an energy ratio of 321x. The ratio is largely due to the memory controller, the DDR3 physical-level interface, on-chip bus access, page activation, etc.…”

Section: Synapses Close To Neuronsmentioning

confidence: 99%

“…We use VCS to simulate the node RTL, an eDRAM model which includes destructive reads, and periodic refresh of a banked eDRAM running at 606MHz (the eDRAM energy was collected using CACTI5.3 [1] after integrating the 1T1C cell characteristics at 28nm [25]), and inter-node communications were simulated using the cycle-level Booksim2.0 interconnection network simulator [10] (Orion2.0 [29] for the network energy model).…”

Section: Measurementsmentioning

confidence: 99%

DaDianNao: A Neural Network Supercomputer

Luo

Liu

et al. 2017

IEEE Trans. Comput.

156

View full text Add to dashboard Cite

Many companies are deploying services largely based on machine-learning algorithms for sophisticated processing of large amounts of data, either for consumers or industry. The state-of-the-art and most popular such machine-learning algorithms are Convolutional and Deep Neural Networks (CNNs and DNNs), which are known to be computationally and memory intensive. A number of neural network accelerators have been recently proposed which can offer high computational capacity/area ratio, but which remain hampered by memory accesses. However, unlike the memory wall faced by processors on general-purpose workloads, the CNNs and DNNs memory footprint, while large, is not beyond the capability of the on-chip storage of a multi-chip system. This property, combined with the CNN/DNN algorithmic characteristics, can lead to high internal bandwidth and low external communications, which can in turn enable high-degree parallelism at a reasonable area cost. In this article, we introduce a custom multi-chip machine-learning architecture along those lines, and evaluate performance by integrating electrical and optical inter-chip interconnects separately. We show that, on a subset of the largest known neural network layers, it is possible to achieve a speedup of 656.63x over a GPU, and reduce the energy by 184.05x on average for a 64-chip system. We implement the node down to the place and route at 28nm, containing a combination of custom storage and computational units, with electrical inter-chip interconnects.

show abstract

“…6T-SRAM suffers from creeping variability [1][2] and reliability [3][4][5] issues, which results in cell instability problems. One transistor and one capacitor DRAM cells (1T1C) struggle to maintain reasonable refresh time [6][7]. Efforts have been made to find new memory solutions, such as capacitor-less cells [8][9][10].…”

Section: Introductionmentioning

confidence: 99%

Thorough Understanding of Retention Time of Z2FET Memory Operation

Duan

Navarro

Cheng³

et al. 2019

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

A recently reported zero impact ionization and zero subthreshold swing device Z2FET is a promising candidate for capacitor-less DRAM memory cell. In memory operation, data retention time determines refresh frequency, and is one of the most important memory merits. In this paper, we have systematically investigated the Z2FET retention time based on a newly proposed characterization methodology. It is found that the degradation of HOLD '0' retention time originates from the Gated-SOI portion rather than the Intrinsic-SOI region of the Z2FET. Electrons accumulate under Front Gate (FG) and finally collapse the potential barrier turning logic '0' to '1'. It appears that Shockley-Read-Hall (SRH) generation is the main source for electrons accumulation. Z2FET scalability has been investigated in terms of retention time. As the Z2FET is downscaled, the mechanism dominating electrons accumulation switches from SRH to parasitic injection of electrons from the cathode. Results show that downscaling of Lg has little effect on data '0' retention, but Lin is limited to ~125nm. An optimization method of the fabrication process is proposed based on this new understanding, and Lin can be further scaled down to 75nm. We have demonstrated by 2D TCAD simulation that Z2FET is a promising DRAM cells candidate particularly for IoT applications.

show abstract

A high-performance, high-density 28nm eDRAM technology with high-K/metal-gate

Cited by 17 publications

References 7 publications

${Z}^{\textsf {2}}$ -FET as Capacitor-Less eDRAM Cell For High-Density Integration

${Z}^{\textsf {2}}$ -FET as Capacitor-Less eDRAM Cell For High-Density Integration

DaDianNao: A Neural Network Supercomputer

Thorough Understanding of Retention Time of Z2FET Memory Operation

Contact Info

Product

Resources

About