A High Performance Hybrid Wave-Pipelined Multiplier

Abstract

The clock period in conventional pipeline scheme is proportional to the maximum delay while in hybrid wave-pipelining it is proportional to the maximum delay difference. An 8×8-bit hybrid wave-pipeline multiplier using carry-save adder technique is described. The multiplier has been designed using TSMC 180nm. The basic cells in multiplier are designed to have small propagation delay and delay variation. The hybrid wave-pipelined multiplier is able to achieve 2.86 billion multiplications per second.

Low‐power 6‐GHz wave‐pipelined 8 b × 8 b multiplier

“…The detailed comparison on critical parameters with other competitive designs is avoided here for the sake of brevity. However, a benchmarking exercise only on speed and power dissipation, with ten recent competitive designs, namely of [1, 3–9, 16, 24] show that the proposed work outperforms all the others. This is because of modified architecture combined with effective wave‐pipelining with pair‐wise multiplication algorithm.…”

“…Multiplication is one of the critical operations in all computation intensive applications [1][2][3][4][5][6][7][8][9]. Low-power consumption is a criterion for many battery operated systems.…”

“…"Wave-pipelining is a design technique for increasing throughput of a digital circuit without introducing pipelining-registers between adjacent combinational logic blocks in the circuit/system" [8]. However, this requires balancing of the delays along all the paths from the input to the output, which are designed for its implementation [8][9][10][11][12][13][14]. Burleson et al [ 10] first proposed a systematic design methodology to this end.…”