A high performance machine paradigm based on auto-sequencing data memory

Hartenstein, Reiner W.; Hirschbiel, A. G.; Riedmuller, M.; Schmidt, K.; Weber, Matthias

doi:10.1109/hicss.1991.183886

Cited by 5 publications

(2 citation statements)

References 11 publications

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“…Along with the systolic array, the concept of data streams has been introduced (by Kung [1987] and others), but usually without explaining how these multiple data streams entering and leaving systolic arrays are generated at run time. Such a distributed memory methodology was popularized two decades after its introduction mostly by Professor Francky Catthoor and his group at IMEC [Catthoor et al 1998] as application-specific distributed memory architectures, also called asM (auto-sequencing memory [Hartenstein et al 1991]), where, instead of a program counter, data counters are used that reside in the memory banks [Herz et al 2002], which really means a new machine paradigm, the antimachine paradigm-a counterpart of the von Neumann paradigm (also see [Hartenstein 2004]). The term data streams for multiple parallel data streams, which we have adopted from the area of systolic arrays, should not be confused with the term stream processing used in the area of multimedia, where it relates to single streams of similar data objects like those known from video processing.…”

Section: Systolic Arrays and Reconfigurable Systemsmentioning

confidence: 99%

Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic

Ayala-Rincón

Llanos

Jacobi

et al. 2006

ACM Trans. Des. Autom. Electron. Syst.

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Many algebraic operations can be efficiently implemented as pipe networks in arrays of functional units such as systolic arrays that provide a large amount of parallelism. However, the applicability of classical systolic arrays is restricted to problems with strictly regular data dependencies yielding only arrays with uniform linear pipes. This limitation can be circumvented by using reconfigurable systolic arrays or reconfigurable data path arrays, where the node interconnections and operations can be redefined even at run time. In this context, several alternative reconfigurable systolic architectures can be explored and powerful tools are needed to model and evaluate them. Well-known rewriting-logic environments such as ELAN and Maude can be used to specify and simulate complex application-specific integrated systems. In this article we propose a methodology based on rewriting-logic which is adequate to quickly model and evaluate reconfigurable architectures (RA) in general and, in particular, reconfigurable systolic architectures. As an interesting case study we apply this rewriting-logic modeling methodology to the space-efficient treatment of the Fast-Fourier Transform (FFT). The FFT prototype conceived in this way, has been specified and validated in VHDL using the Quartus II system.

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Section: Systolic Arrays and Reconfigurable Systemsmentioning

confidence: 99%

Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic

Ayala-Rincón

Llanos

Jacobi

et al. 2006

ACM Trans. Des. Autom. Electron. Syst.

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“…Not only for economic reasons it is overdue to develop a widely spread awareness on this revolutionary development. In contrast to the von Neumann paradigm the anti machine's sequencer (data counter) has moved to the memory (as part of an asM [25] [41] [42] [44], an auto-sequencing memory bank), whereas the DPU of the anti machine has no sequencer. The anti machine paradigm also supports multiple data streams by multiple asMs providing multiple data counters.…”

Section: The Anti Machinementioning

confidence: 99%

The digital divide of computing

Hartenstein

2004

Proceedings of the 1st Conference on Computing Frontiers

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This presentation urges for creating more awareness of the impact of configware engineering onto embedded system development and examines the requirements of overdue CSE curricular upgrades. Because of the impact of reconfigurable computing, configware engineering has proceeded from niche to mainstream. Morphware has become an essential and indispensable ingredient in SoC (System on a Chip) design and beyond. It turns embedded system design from hardware / software co-design into configware / software co-design [1] [2] [3] [4]. This hot development, supported by the fastest growing segment of the semiconductor market [5], provides morphware [6] [7] as an alternative RAMbased "programmable" (more precisely called: "reconfigurable") platform for parallelism avoiding the limitations of classical high performance computation [8] [9] [10] caused by the von Neumann paradigm [11] [12] [13]. The digital divide of computing determines who is qualified to take off toward new horizons in high performance computing, and, who is not. Currently the typical CS graduate is not.

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Reconfigurable computing: a new business model-and its impact on SoC design

Hartenstein

Proceedings Euromicro Symposium on Digital Systems Design

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Making gate arrays obsolete, FPGAs are successfully proceeding from niche to mainstream. Like microprocessor usage, FPGA application is RAM-based, but by structural programming (also called "(rejconfiguration'3 instead of procedural programming. Now both. host and accelerator are RAM-based and as such also available on the same chip: a new approach to SoC design. Now also accelerator definition may be -at least partlyconveyed from vendor site to customer site. A new business model is needed. But this paradigm switch is still ignored: FPGAs do not repeat the RAM-based success story of the sofhvare industry. There is not yet a configware industry, since mapping applications onto FPGAs mainly uses hardware synthesis methods. From a decade of world-wide research on Reconfigurable Computing another breed of reconfigurable platforms is an emerging future competitor to FPGAs. Supporting roughly single bit wide configurable logic blocks (CLBs) the mapping tools are mainly based on gate level methodssimilar to CAD for hardwired logic. In contrast to this fine-grained reconfigurabiliy, the Reconfigurable Computing scene uses arrays of coarse-grained reconfigurable datapath units (rDPUsj with drastically reduced reconfigurability overhead: to directly configure high level parallelism.But the "yon Neumann" paradigm does not support sofl datapaths because "instruction fetch" is not done at run time. and, since most reconfigurable computing arrays do not run parallel processes, but multiple pipe nemorks instead. To introduce the new business model to cope with the current accelerator design crisis a transition from CAD to compilation is needed, and from hardware/sofhvare co-design to configware/sofhvare co-compilation. The paper illustrates such a roadmap to reconfigurable computing, supporting the emerging trend to platform-based SoC design.

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A high performance machine paradigm based on auto-sequencing data memory

Abstract: Abstract.This paper introduces a novel (non-von Neumann)

Cited by 5 publications

References 11 publications

Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic

Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic

The digital divide of computing

Reconfigurable computing: a new business model-and its impact on SoC design

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