A high performance multiply-accumulate unit with double carry-save scheme for 6-input LUT based reconfigurable systems

Cini, Ugur; Kurt, Olcay

doi:10.1109/eleco.2015.7394625

Cited by 1 publication

(1 citation statement)

References 9 publications

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“…To increase the speed of operation, even more, a strategy to compact the "partial product using interleaved adders" and a "modified hybrid partial product reduction tree (PPRT)" scheme is proposed. A double carry-save addition algorithm is proposed in [26], where its prototype is also verified on a six-input Look-up Table (LUT) based Field Programmable Gate Array (FPGA). In 2016, an "embedded logic full adder (PRO-FA)" was presented in [14], which offers better improvements on the basic design constraint.…”

Section: Introduction To Multiply and Accumulate (Mac) Architecturementioning

confidence: 99%

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

Sarma¹,

Bhargava²,

Kotecha³

2022

Computers, Materials &Amp; Continua

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In the era of digital signal processing, like graphics and computation systems, multiplication-accumulation is one of the prime operations. A MAC unit is a vital component of a digital system, like different Fast Fourier Transform (FFT) algorithms, convolution, image processing algorithms, etcetera. In the domain of digital signal processing, the use of normalization architecture is very vast. The main objective of using normalization is to perform comparison and shift operations. In this research paper, an evolutionary approach for designing an optimized normalization algorithm is proposed using basic logical blocks such as Multiplexer, Adder etc. The proposed normalization algorithm is further used in designing an 8 × 8 bit Signed Floating-Point Multiply-Accumulate (SFMAC) architecture. Since the SFMAC can accept an 8-bit significand and a 3-bit exponent, the input to the said architecture can be somewhere between −(7.96872) 10 to + (7.96872) 10 . The proposed architecture is designed and implemented using the Cadence Virtuoso using 90 and 130 nm technologies (in Generic Process Design Kit (GPDK) and Taiwan Semiconductor Manufacturing Company (TSMC), respectively). To reduce the power consumption of the proposed normalization architecture, techniques such as "block enabling" and "clock gating" are used rigorously. According to the analysis done on Cadence, the proposed architecture uses the least amount of power compared to its current predecessors.

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Section: Introduction To Multiply and Accumulate (Mac) Architecturementioning

confidence: 99%

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

Sarma¹,

Bhargava²,

Kotecha³

2022

Computers, Materials &Amp; Continua

View full text Add to dashboard Cite

show abstract

A high performance multiply-accumulate unit with double carry-save scheme for 6-input LUT based reconfigurable systems

Cited by 1 publication

References 9 publications

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

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