A High-Performance Processing-in-Memory Accelerator for Inline Data Deduplication

Lee, Young Seo; Kim, Kyung Min; Lee, Ji Heon; Choi, Jeong Hwan; Chung, Sung Woo

doi:10.1109/iccd46524.2019.00077

Cited by 3 publications

(1 citation statement)

References 29 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This is mainly because the power consumption per synapse is very small level of 0.01 pW. Note that a single central processing unit (CPU) for the conventional computer system shows a high-power consumption of 100 W approximately, which is 10 times higher compared to the total power consumption of the brain [14], [15].…”

Section: Introductionmentioning

confidence: 99%

A Geometrical Optimization Rule of the Synaptic Pass-Transistor for a Low Power Analog Accelerator

et al. 2022

View full text Add to dashboard Cite

We present a simulation framework on a geometrical optimization rule of the synaptic passtransistor (SPT) for a low power analog accelerator (AA). Here, the SPT is a synaptic transistor (Syn-Tr) in series with a load resistor to be scaled with respect to a geometrical ratio between a channel length and width of the Syn-Tr. When only the load resistance is increased for the reduction of the power consumption of the SPT, a synaptic characteristics (e.g. a synaptic dynamic ratio, DR w ) is hard to be maintained. To overcome this, the channel geometrical ratio and scaling factor of the load resistance are required to be increased equally, thus a geometrical optimization rule. Here, the load resistance is equivalent to a geometric mean where two extreme cases of the synaptic full facilitation and full depression are considered. To verify the proposed rule, we perform a semiconductor device simulation for a static and pulsed characteristics of the SPT. When the SPT is scaled based on the geometrical optimization rule, from the simulation results, it is found that the static-power consumption is decreased while maintaining the DR w . As a trade-off relation, however, the noise power-spectral-density is found to be increased due to a higher thermal noise associated with a higher total resistance of the scaled SPT. Here, the increased noise power-spectral-density of a single SPT may affect the performance of the AA based on the SPT-array, so we also show a crossbar simulation, checking the classification accuracy against a standard dataset (e.g. MNIST).

show abstract

Section: Introductionmentioning

confidence: 99%