A high‐performance processor for optimal ate pairing computation over Barreto–Naehrig curves

Xie, Yujun; Wang, Bin; Zhang, Lijun; Zheng, Xin; Lin, Xiaoling; Xiong, Xiaoming; Liu, Yuan

doi:10.1049/cds2.12116

Cited by 3 publications

(1 citation statement)

References 27 publications

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“…This design has a reasonable increase in area with a higher number of DSP blocks, making it limited to integration on high-resource FPGA boards, unlike our designs which can be implemented on large FPGA circuits. In [55], a highperformance processor for optimal Ate pairing on BN-curves is proposed, exploiting parallelism and pipeline at various levels of the algorithm. However, this design has a higher area occupation with a higher number of DSP blocks and is not suitable for restricted environments.…”

Section: B Discussionmentioning

confidence: 99%

Flexible and Parallel Architectures for Optimal Ate pairing on FPGA

Oussama

Akil

Koudil

et al. 2022

Preprint

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This paper presents three approaches for the implementation of Optimal Ate pairing based on Jacobean coordinates, over Barreto-Naehrig curves, targeting the 128 bits security level, in Genesys board. The first approach is a fully software implementation using MicroBlaze processor. The second approach is software/hardware implementation, in which the most useful operations in \({\varvec{F}}_{\varvec{p}}\) and \({\varvec{F}}_{{\varvec{p}}^{2}}\) are coded as intellectual property cores around the Microblaze. The third approach is based on the second in which we exploit the parallelism that exists to compute Optimal Ate pairing. The integration of multi-MicroBlaze processor in single architecture allows not only the flexibility of the overall system but also the parallelism to speed up pairing. Various techniques and parameters are used and combined to compute Optimal Ate in efficient way, namely: Montgomery modular multiplication, Karatsuba method, Jacobean coordinate, Complex method for squaring, Sparse multiplication, squaring in the cyclotomic subgroup \({\varvec{G}}_{\varvec{\varphi }6}\left({\varvec{F}}_{{\varvec{p}}^{12}}\right)\) and addition chain method. Our flexible and parallel systems are dedicated for restricted environment resources with a reasonable execution time.

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Section: B Discussionmentioning

confidence: 99%

Flexible and Parallel Architectures for Optimal Ate pairing on FPGA

Oussama

Akil

Koudil

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

Novel area-efficient and flexible architectures for optimal Ate pairing on FPGA

Azzouzi,

Anane,

Koudil

et al. 2023

J Supercomput

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GAPS: GPU-accelerated processing service for SM9

Xu,

Ma,

Zhang

2024

Cybersecurity

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SM9 was established in 2016 as a Chinese official identity-based cryptographic (IBC) standard, and became an ISO standard in 2021. It is well-known that IBC is suitable for Internet of Things (IoT) applications, since a centralized processing of client data (e.g. IoT cloud) is often done by gateways. However, due to limited computation resources inside IoT devices, the performance of SM9 becomes a bottleneck in practical usage. The existing SM9 implementations are often CPU-based, with relatively low latency and low throughput. Consequently, a pivotal challenge for SM9 in large-scale applications is how to reduce the latency while maximizing throughput for numerous concurrent inputs. After a systematic analysis of the SM9 algorithms, we apply optimization techniques including precomputation, resource caching and parallelization to reduce the overhead of SM9. In this work, we introduce the first practical implementation of SM9 and its underlying curve on GPU. Our GPU implementation combines multiple algorithms and low-level optimizations tailored for GPU’s single instruction, multiple threads architecture in order to achieve high throughput for SM9. Based on these, we propose , a high-performance Cryptography as a Service (CaaS) for SM9. adopts a heterogeneous computing architecture that flexibly schedules the inputs across two implementation platforms: a CPU for the low-latency processing of sporadic inputs, and a GPU for the high-throughput processing of batch inputs. According to our benchmark, only takes a few milliseconds to process a single SM9 request in idle mode. Moreover, when operating in its batch processing mode, can generate 2,038,071 private keys, 248,239 signatures or 238,001 ciphertexts per second. The results show that scales seamlessly across inputs of different sizes, preliminarily demonstrating the efficacy of our solution.

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A high‐performance processor for optimal ate pairing computation over Barreto–Naehrig curves

Cited by 3 publications

References 27 publications

Flexible and Parallel Architectures for Optimal Ate pairing on FPGA

Flexible and Parallel Architectures for Optimal Ate pairing on FPGA

Novel area-efficient and flexible architectures for optimal Ate pairing on FPGA

GAPS: GPU-accelerated processing service for SM9

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